Finite state machine (summarizing)

AI Thread Summary
The discussion focuses on creating a Mealy state diagram for a finite state machine (FSM) with one serial input and four outputs. The user seeks assistance in understanding how the FSM reacts to specific inputs, particularly how the outputs change based on the clocked bits. It is suggested that the outputs are a direct function of the input bits, prompting the user to consider the type of logic gate that could achieve the desired output. The conversation emphasizes the importance of recognizing the function performed on the serial input string. Overall, the thread aims to clarify the relationship between input sequences and their corresponding outputs in the FSM design.
axcelenator
Messages
33
Reaction score
0
Hello, I have an FSM which has 1 serial input and 4 outputs. The FSM must react to the table attaced in file.
I can see that if the input is(for example)4 the output is 7(+3).
I have to draw a state diagram(mealy). I can't solve it. Need some help
Thanks
 

Attachments

  • FSM.png
    FSM.png
    27.5 KB · Views: 489
Physics news on Phys.org
I take it that arrow coming into the top is your clock.

Have you recognized the function being performed on the serial string?
If you haven't, look closely. What would you expect if you clocked in 1, 0, 1, 0?

Since the four outputs are a function of the four bits being clocked in, what do you need to do with those input bits?
Let's say that the input/output list looked like this:
0,0,0,0 => 0 0 0 0
0,0,0,1 => 0 0 0 1
0,0,1,0 => 0 0 1 0
0,0,1,1 => 0 0 1 1
0,1,0,0 => 0 1 0 0
... => ...
What kind of gate would do that for you?
 
Back
Top