FPGA Programming: Mechanism for Setting Transistors

[antonantal]

What is the mechanism used for programming FPGAs? Is it the same as for EPROMs?
I know (although not sure this is correct either) that in EPROMs, for setting a transistor to "1" a control gate is used which is placed in the oxide layer of the MOS transistor and by applying a voltage between the drain and the control gate you will charge the control gate (for NMOS) with electrons (like the "-" plate of a capacitor) ,and thus increase the threshold voltage of the transistor which therefore will not conduct regardless of the voltage you apply on the gate.

 

[berkeman]

Most FPGAs are volatile. After a reset, they read in their settings from an external serial JTAG memory device like a serial ROM or Flash. Is that what you are asking? There's probably a lot more info at Xilinx's website that can help.

 

[antonantal]

No. I'm just curious how are the transistors inside a FPGA set to "1" and then how are they reset. I can't seem to find a detailed (transistor level) description of how FPGAs work.

 

[Kenneth Mann]

There are several books on the subject. One example is "VHDL for Programmable Logic" by Kevin Skahill (Cypress Semiconductor). Note that it is oriented toward VHDL programming of FPGAs, CPLDs, etc; but it also describes the inner workings of FPGAs.

Essentially, an FPGA is a large set of programmable logic blocks on a chip, usually centered around "Look-Up Tables" (LUTs), often followed by multiplexers and latch arrays. By combining these, we can create an almost endless array of logic functions, simply by entering our logic choices into the LUTs and setting up steering paths to and from these blocks. This programming is controlled in the devices (usually) by a series of (semi-Hidden) RAM arrays that make up the look-up tables and others that control steering of the Multiplexers and the routing between the various logic blocks. (Ie., there are a lot more gates on the FPGA than just those that make up the advertised Logic Block components.) As berkeman stated, the JTAG input is used to load the programmed information into the internal control memory of these volatile devices. (Not all FPGAs etc. need be volatile, but this is generally the rule. They could also be programmed with internal EPROM, etc.)

KM

 

[chroot]

Most fast FPGAs are nothing more than SRAM-based lookup tables connected through multiplexers and routing resources like buffers. When they lose power, they lose the contents of their SRAM.

- Warren

 

[antonantal]

Thanks. If the bits are set like in a SRAM than I got the picture.