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Hanging pins

  1. Dec 3, 2007 #1
    Hi everyone,
    I am not getting a hang of the potential at hanging pins. Here a few stuff i did which raised this doubt:

    1. In a microcontroller i wrote a program to input data to a port. The input was through switches one ended of which was grounded. Hence if switch is on then, the controller pin is grounded, else if off, it is hanging. I initially assumed that the state of hanging pin is logc 0, but it didnt work. i then assumed that the state would be logic 1 , it worked.

    2. The same goes for an comparator chip, i tested.

    3. Also in JFETs in our analysis of calculating the gate to source voltage(Vgs), we consider Vgs = - ( Vsource). cause the input impedance of JFET is very high and hence current through Rg( gate resistance) is 0.
    Then what is the need of putting Rg , as putting Rg will result in lowering of input impedance of the JFET amplifier, as a whole? Cant we take out Rg, as Vgs remains unaffected, and hence both the large and small signal analysis.

    Explanation??
     
  2. jcsd
  3. Dec 3, 2007 #2

    berkeman

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    Staff: Mentor

    You must always do something with CMOS inputs. It is very bad practice to leave them open, for two main reasons. First, when the input to a CMOS gate is floating, the pin can float to mid-rail, and that turns on both the input pullup and pulldown stages some, which causes a parasitic current to flow from Vdd to Vss. In a low power circuit, this parasitic current can be more than the whole rest of the cirucuit is consuming -- that's a very bad thing. Second, with the input floating, it can be influenced by small E field changes in the area, and can cause the gate to switch noisily and generally rattle around, creating noise on the PCB.

    Always terminate unused CMOS inputs to Vdd or Vss, optionally through a resistor. Note that with many uCs and CPLDs and FPGAs, you can enable on-chip pullup (or pulldown) resistors, which saves you having to use an external resistor. Also, your switch input circuit should have a pullup resistor, if the switch grounds the input.
     
  4. Dec 12, 2007 #3
    How can the pin float to mid-rail region? Say midrail is between 2V to 3V, the circuit noise , E interference, cannot produce a voltage in the hanging pin of more than a few millivolts.
     
  5. Dec 12, 2007 #4

    berkeman

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    Well, static charge in the air is one way. I've seen floating inputs change the output state, based on how close you move your hand to the PCB! That one had me going for a while, until I realized that there were some unconnected inputs on that hand-built prototype board. 50/60Hz E-field noise from nearby AC Mains circuitry is another way.
     
  6. Dec 12, 2007 #5
    Did this really happen with digital circuits? I have experienced similar problems with analog circuits, and always thought it was because by moving hand to PCB, we are adding capacitance to it, between the circuit and earth ground. For example moving your hand over a radio receiver, will result in an observable noise from the speakers.
     
    Last edited: Dec 12, 2007
  7. Dec 12, 2007 #6

    berkeman

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    Yes, that example was a 74HC245 buffer circuit driving some LEDs, but I'd left 4 of the inputs floating. Waving my hand near the circuit made those 4 LEDs change ON/OFF/ON, and I could make them buzz with certain hand positions.
     
  8. Dec 12, 2007 #7
    Ok. But why doesnt the same phenomenon affect circuits which are all connected, and no pin is left hanging. Say i am driving a transistor gate with a micro controller. The current sourced by the controller is low. So isnt there a good chance of static, E interfering with the digital circuitry?
     
  9. Dec 12, 2007 #8

    berkeman

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    When an input is connected to a logic output, it is being driven high or low by a low impedance, typically in the few tens of Ohms. Even when an input is pulled high or low by a passive resistor, that resistance is typically in the 1k to 10k Ohm range, which is plenty to hold the input at a rail. The issue is the very high input impedance of the CMOS inputs themselves (small capacitance with a tiny leakage current) -- when they are left disconnected, even small nearby influences can change the input gate voltages.
     
  10. Dec 12, 2007 #9
    During development of a product we had left the window on an EPROM uncovered because the firmware was changed routinely. Some upper address pins were accidentally left open and when the EPROM was in the dark it the whole thing would crash. When the window was exposed to light everything would work fine. Leaving pins floating in digital circuits is BAD BAD practice.
     
  11. Dec 20, 2007 #10
    But consider a JFET amplifier , in any bias configuration. The input is applied at the gate , which has an large resistance Rg of the order of 1Mohm going to the ground (as good as an hanging pin). Though this may not be an digital circuit, wont the same static charge stuff, cause votage fluctuations? The source voltage used is in the order of millivolts.
     
  12. Dec 20, 2007 #11

    berkeman

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    The source voltage is not the issue -- the issue is the source impedance. If it is very high, then yes, you are going to have noise problems. Johnson noise is an important consideration in the design of FET amplifiers:

    http://en.wikipedia.org/wiki/Thermal_noise
     
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