Hi everyone, I am not getting a hang of the potential at hanging pins. Here a few stuff i did which raised this doubt: 1. In a microcontroller i wrote a program to input data to a port. The input was through switches one ended of which was grounded. Hence if switch is on then, the controller pin is grounded, else if off, it is hanging. I initially assumed that the state of hanging pin is logc 0, but it didnt work. i then assumed that the state would be logic 1 , it worked. 2. The same goes for an comparator chip, i tested. 3. Also in JFETs in our analysis of calculating the gate to source voltage(Vgs), we consider Vgs = - ( Vsource). cause the input impedance of JFET is very high and hence current through Rg( gate resistance) is 0. Then what is the need of putting Rg , as putting Rg will result in lowering of input impedance of the JFET amplifier, as a whole? Cant we take out Rg, as Vgs remains unaffected, and hence both the large and small signal analysis. Explanation??