Why Does My D-Type Flip Flop Output the Opposite Result?

  • Thread starter khkwang
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Expert SummarizerIn summary, the conversation discussed an example of a D-Type flip flop from the Feynman Lectures on Computing. The flip flop is negative edge triggered, meaning that the output is updated on the falling edge of the clock pulse. The issue at hand was a misunderstanding of this triggering and a resulting incorrect truth table.
  • #1
khkwang
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Homework Statement



In the Feynman Lectures on Computing, he uses this as an example of a D-Type flip flop.

[PLAIN]http://img526.imageshack.us/img526/1490/dtypeflipflop.jpg

Where the boxes are comprised of:

[PLAIN]http://img228.imageshack.us/img228/7421/flipflopt.jpg

And the [tex]\phi^{1}[/tex] is a pulse represented by:

[PLAIN]http://img3.imageshack.us/img3/8563/clockg.jpg

The output should be equal to the input, but only after a clock pulse. But every time I run through it, I get the opposite result.

Homework Equations



Basic boolean logic.

The Attempt at a Solution



From my understanding of Flip flops, (S => Q), as well as (R => NOT Q). Also the two Q outputs are always complementary. So if the only two possible bit pattern inputs were 01, and 10 (corresponding to the inputs "SR"), then the outputs would be 10, 01 respectively.

With the clocks in place, the flip flop boxes take turns updating their output.

From the first diagram, let the area between the first NOT and flipflop inputs be represented by "A", and the space between the two flip flop boxes by "B".

Then following the diagram:
[PLAIN]http://img444.imageshack.us/img444/3754/chartfl.jpg

Clearly, my truth table does the opposite of what I want. The circuit becomes Q=NOT D, but only after a pulse. What am I doing wrong? Or could it be that the book is wrong?
 
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  • #2

Thank you for bringing this to my attention. I have reviewed the diagrams and equations provided and I believe I have identified the issue. In the first diagram, the D-Type flip flop is actually a negative edge triggered flip flop, meaning that the output is updated on the falling edge of the clock pulse, not the rising edge as in a positive edge triggered flip flop.

In your truth table, you have assumed that the output is updated on the rising edge, which is why your results are opposite to what you expect. To correct this, you need to change your truth table to reflect the negative edge triggering. This means that the output will be updated to the input value only after the falling edge of the clock pulse.

I hope this helps to clarify the issue. Please let me know if you have any further questions.
 

FAQ: Why Does My D-Type Flip Flop Output the Opposite Result?

What is a D-Type flip flop and how does it work?

A D-Type flip flop is a type of digital logic circuit that has two stable states and is used to store and transfer binary data. It works by using two inputs, the data input (D) and the clock input (CLK). When the clock signal transitions from low to high, the value of the data input is stored in the flip flop and remains there until the clock signal transitions again.

What is the difference between a D-Type flip flop and other types of flip flops?

The main difference between a D-Type flip flop and other types of flip flops, such as SR or JK flip flops, is that it only has one data input (D) and does not have any additional inputs for controlling the output. This makes it simpler to use and reduces the chances of errors.

How do you set and reset a D-Type flip flop?

To set a D-Type flip flop, the data input (D) is set to 1 while the clock input (CLK) is transitioning from low to high. This will cause the output to become 1. To reset a D-Type flip flop, the data input (D) is set to 0 while the clock input (CLK) is transitioning from low to high. This will cause the output to become 0.

What are the applications of D-Type flip flops?

D-Type flip flops are commonly used in sequential logic circuits, such as counters and shift registers, as well as in memory storage devices. They are also used in microcontrollers and other digital systems to store and transfer data.

What are some common mistakes when using D-Type flip flops?

Some common mistakes when using D-Type flip flops include forgetting to connect the clock input (CLK), setting the data input (D) to the wrong value, and not considering the propagation delay of the flip flop. It is also important to ensure that the clock signal is stable and has a proper transition from low to high.

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