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Help with PLL circuits

  1. Oct 7, 2013 #1
    Hi guys,

    How are you all? I am trying to build to a PLL circuits. As part of the circuit, I will need an offset adder, integrator, rectifier, and another stage of offset adder.

    I havent done circuits for very long time. So please bear with me if Im mistaken.

    Appreciate your help.

    I have designed the first stage offset adder and integrator.

    Please see attached diagrams. Schematic 1 is the circuit for offset adder which basically a summing amplifier, and then the second stage op-amp is the integrator.

    The AC source with 1 Vac, is passed through the R3 and R1, R3 will later be a variable resistor when I transfer this to PCB.

    From the diagram, I dont understand how the 5V added by V2 becomes 2.5V at the output of U1 (first Op-amp). I tried calculating it out, but could not get the exact point. Please advice.

    Then, at the second stage. If you see the frequency response diagram. The 3dB is approximately at 200 kHz. But by using 1/2[tex]\prod[/tex]RC formula, R=R3 and C=C1, which are 1 kohm and 50 pF, respectively, the cutoff should be approximately 3.1 MHz. So I dont really get it. Please advice if Im in the right direction, or the equivalent circuit calculation is wrong.

    Please point where Im going wrong. I have also attached the time domain graph.

    Thank you so much.

    Attached Files:

    Last edited by a moderator: Oct 7, 2013
  2. jcsd
  3. Oct 7, 2013 #2


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    Gold Member

    The numbers don't make any sense to me. Did you forget power to the opamps?
  4. Oct 8, 2013 #3
    Thanks. I fixed it, its the variable resistor. Thanks again.

    Between, I have found the XR-2211A that could do the job :

    See attached datasheet.


    The datasheet provides the circuit construction for tone detection, and I need that. But however, it is unclear how could I tap out the VCO output, cause that is what I need, I need the locked VCO output.

    Please anyone, advice me, I really dont understand.
  5. Oct 8, 2013 #4


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    Staff: Mentor

    I'm not familiar with that IC, but looking at the datasheet I think you could tap the waveform at pin 13 or 14 and use a high-impedance analog buffer/comparator to square it up.
  6. Oct 20, 2013 #5
    I choose not to use the IC. I built my own circuit. Thanks NascentOxygen.

    I have built the circuit in practical. Its working fine. But I have a small problem, please see the attached schematic.

    So the signal goes through a summing amp, integrator, full wave rectifier and final summing amp. All the sections are working fine. But after full wave rectifier (Op amp U4), there a is a DC offset. I dont want that DC offset. Because I would like to add DC through the final stage of summing amp from 0V to any arbitrary +V. So how can I remove the DC, I dont want any inline capacitor. Im thinking of buffer, will that be the correct move?

    Please advice.

    Attached Files:

  7. Oct 21, 2013 #6


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    Staff: Mentor

    You invented this design yourself, did you? Or what is it based on?

    That DC component is a consequence of the preceding stages.

    I'm not sure this is a PLL. Where is your phase detector? Where is your VCO?
  8. Oct 21, 2013 #7
    Hi NascentOxygen. Yes. I combined bits and pieces from here and there. I have external mixer and VCO. The subsequent mixed baseband signal error signal will go through this circuit.

  9. Oct 21, 2013 #8


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    Staff: Mentor

    I think you need to explain what each OP-AMP block does here. Where will the error signal connect into this circuit? Is the 100k signal source part of this, and is it sinusoidal or square wave? What function does the fast integrator perform?
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