I'm having trouble with the following VHDL code: Code (Text): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity circuit is port (a, b, c: in std_logic; f1, f2, f3, f4, f5, f6: out std_logic); end circuit; architecture Structural of circuit is component NOT1 port(in1, in2, in3, in4: in std_logic; out1, out2, out3, out4: out std_logic); end component; component AND1 port(in1, in2, in3, in4, in5, in6, in7, in8: in std_logic; out1, out2, out3, out4: out std_logic); end component; component OR1 port(in1, in2, in3, in4, in5, in6, in7, in8: in std_logic; out1, out2, out3, out4: out std_logic); end component; signal anot, bnot, cnot, or3, or8, or11, and8, or6, and6 : std_logic; begin G0: NOT1 port map (in1 => a, out1 => anot, in2 => b, out2 => bnot, in3 => or3, out3 => f1, in4 => or3, out4 => f4); G1: AND1 port map (in1 => c, in2 => or11, out1 = f3, in3 => a, in4 => bnot, out2 => and8, in5 => a, in6 => or6, out3 => f2, in7 => anot, in8 => b, out4 => and6); G2: OR1 port map(in1 => and8, in2 => and6, out1 = or11, in3 => bnot, in4 => c, out2 => or8, in5 => anot, in6 => bnot, out3 => or3, in7 => bnot, in8 => c, out4 => or6); end Structural; The compiler says that 'out1' is an undefined symbol in line 30 (G1). I have each gate defined separately, and all port definitions match between the gates and the whole circuit. The individual gates run with no problems, so I don't understand why the program chokes when I try to string them together. Renaming the outputs in G1 and the AND gate have no effect. I'd appreciate any pointers on where I'm going wrong. Everything's fine when I comment out G1 and G2.