Looks like this isn't homework and not coursework you have done yet, so I'll just show you a way of doing it.
I haven't heard of "just have fun with it" as a method of teaching.
If you are not given any design requirements, you can just make up some of your own.
Assume a 1K load resistor. Assume a 10 volt supply voltage. My choice.
Now, if this is going to be a linear amplifier, the voltage across the FET should be about half the supply voltage. So about 5 volts.
This means the voltage across the 1K resistor is 5 volts. So the drain current is 5 mA.
Now you do have to go to data sheets. What voltage does the FET have to have on its gate to produce 5 mA of drain current? Suppose you look it up and it is -1.7 Volts.
You can either find -1.7 volts from somewhere (not easy if you have a +10 volt supply) or you can put in a source resistor that will give +1.7 volts at the source relative to the gate.
You know the drain current is 5 mA so the source resistor is 1.7/.005 =... ohms?
You can increase the supply voltage to 11.7 to compensate for this extra 1.7 volts if you like, or you could recalculate to allow for the slightly reduced drain current. I'd increase the supply voltage.
This source resistor will reduce the gain of the amplifier if you leave it like that, so it should have a capacitor across it. The capacitor should have a reactance of 10% of the source resistance at the lowest frequency being amplified.
Now, all you have to do is make sure there is a suitable resistor from the gate to ground. 100 K is a good value. It isn't critical, but there has to be something there.
Notice that I did not consult the data sheets for an MPF102 so you should do this to obtain an actual bias value.
I found the following site that looks helpful as well:
http://www.rason.org/Projects/jfetamp/jfetamp.htm
They may cover some points I have forgotten to mention.