How do you guys put gates and kmaps into tech papers?

  • Thread starter seang
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In summary, the conversation discusses different options for creating Kmap images and gate images for a paper. Suggestions include using software like OrCAD or PowerPoint, or getting creative with Paint. The speaker also mentions using Word's drawing tools to create rectangles for the K-map.
  • #1
seang
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Is there anything online or elsewhere which I can use to create Kmap images? and gate images? I'm writing a paper and I hate to just draw them on there.
 
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  • #2
I would just do them in OrCAD and cut and paste them into Word for the report. I don't know offhand if there is a student edition of OrCAD or PSPICE, though. Alternately, does PowerPoint have a logic symbol library maybe? Or you could draw your own symbols in PowerPoint and re-use them.
 
  • #3
If nothing else, get creative with Paint. You only have to draw them once. Just use what you've made as a library.

Edit: This may be simple enough with a handful of gates, but obviously has its limitations.
 
  • #4
For Kmaps, I would make a Table in MS Word with all the right values, then hit print screen and paste it in paint and use different colored curved rectangles to show the groupings.

As for gates, if you mean schematics, I did all those in paint too, my professor was impressed that I did it this way actually
 
  • #5
Number2Pencil said:
For Kmaps, I would make a Table in MS Word with all the right values, then hit print screen and paste it in paint and use different colored curved rectangles to show the groupings.

You can also skip the Paint rectangle step if you draw the rectangles in Word. Check out the drawing tools, and look for the rectangle tool. After you draw the rectangle, you make the Fill = None, and you can change the color and line width of the rectangle to make it stand out on the K-map.
 

1. How do you determine which gates and kmaps to include in a tech paper?

The gates and kmaps included in a tech paper are typically determined by the specific research topic and objectives of the paper. The researcher must consider which gates and kmaps are relevant and necessary to support their arguments and conclusions.

2. What is the purpose of including gates and kmaps in a tech paper?

Gates and kmaps are used in tech papers to provide a visual representation of complex logical circuits and functions. This allows readers to better understand the concepts being discussed and supports the evidence and analysis presented in the paper.

3. How do you create or generate gates and kmaps for a tech paper?

Gates and kmaps can be created using various software tools, such as logic gate simulators or programming languages like Verilog or VHDL. These tools allow researchers to design and test different circuits and generate the corresponding gates and kmaps.

4. How do you properly cite gates and kmaps in a tech paper?

Gates and kmaps should be cited like any other source used in a tech paper. This typically involves including the author's name, publication date, and source information (e.g. journal or conference). Additionally, the specific circuit or function represented by the gates and kmaps should be mentioned in the citation.

5. Are there any limitations or drawbacks to using gates and kmaps in a tech paper?

While gates and kmaps can be useful in illustrating complex concepts, they may also have limitations in representing certain types of circuits or functions. Additionally, the use of these visual aids may not always be necessary or appropriate, depending on the focus and scope of the tech paper.

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