How to measure voltage rise delay and fall delay?

[6021023]

In Cadence we built a CMOS inverter. I made a transient response graph showing the input and output voltage waveforms. We're supposed to measure rise delay and fall delay of the output voltage. How do I do this? I heard from someone else that it's where the graphs cross 1.5V, but I'm still not exactly sure how to measure it.

 

[berkeman]

In Cadence we built a CMOS inverter. I made a transient response graph showing the input and output voltage waveforms. We're supposed to measure rise delay and fall delay of the output voltage. How do I do this? I heard from someone else that it's where the graphs cross 1.5V, but I'm still not exactly sure how to measure it.

The rise and fall times are usually measured between the 10% and 90% points on the waveform. That is, the time between when the waveform makes it to 0.1Vdd and to 0.9Vdd for the rising edge, and similarly on the falling edge.

This paper (found with googling CMOS Inverter Risetime) has a nice treatment in general of CMOS inverter design:

http://www.ee.mut.ac.th/home/theerayod/lecture_files/EEET0413/Lecture 4 - CMOS Inverter.pdf

.

 

[vk6kro]

We're supposed to measure rise delay and fall delay of the output voltage.

This is a bit ambiguous. It could mean the propagation delay through the inverter or it could mean the rise and fall times of the output waveform.

So, I'll cover both.

See this diagram:

The two waveforms at the left are the input (top) and output (bottom) as viewed on a dual trace oscilloscope. The output will be delayed slightly due to the internal operation of the inverter chip. You measure this on any reasonably vertical portion of both waveforms provided it is the equivalent point on each graph, allowing for the inverting action of the inverter..
This is just to avoid errors due to rounded corners etc.

Rise and fall times are the times it takes for the waveforms to go from 10 % of the full amplitude to 90 % of full amplitude (or the other way around for falling waveforms).
This is shown on the right two diagrams.