Investigating the Effects of a Common Emitter Amplifier

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Discussion Overview

The discussion revolves around the analysis of a common emitter amplifier circuit, focusing on the effects of load impedance on output voltage and the discrepancies between calculated and simulated results. Participants explore the implications of circuit modifications on AC and DC gain, as well as the behavior of voltage divider biasing.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • One participant describes a common emitter amplifier setup with a specific input voltage and frequency, noting an initial AC and DC gain of -10 and the goal to increase AC gain to -50 by adding components.
  • Concerns are raised about observed non-linearity in the AC gain and the unexpected drop in output voltage after connecting a load impedance.
  • Another participant asks for clarification on the difference between the emitter voltage (##V_{E}##) and output voltage (##V_{out}##) when the load impedance is not connected, and how to calculate the voltage divider bias with the load connected.
  • There are requests for simulation results and circuit diagrams to better understand the discrepancies in voltage calculations.
  • Participants discuss the value of the load resistor R10, with some suggesting it may have been misidentified as 1 milliohm instead of 1 megaohm.

Areas of Agreement / Disagreement

Participants express uncertainty regarding the calculations and results from simulations, with no consensus reached on the reasons for the discrepancies or the correct approach to voltage calculations.

Contextual Notes

Participants mention specific values and configurations that may affect the outcomes, such as the frequency of the high pass filter and the assumptions regarding load resistor values. There are indications of unresolved mathematical steps and dependencies on circuit definitions.

Who May Find This Useful

This discussion may be of interest to those studying or working with amplifier circuits, particularly in the context of common emitter configurations, as well as individuals seeking to understand the effects of load impedance on circuit behavior.

PhysicsTruth
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Thread moved from the technical forums to the schoolwork forums
Summary:: Using a common emitter amplifier to pump up the input voltage, and studying the effects henceforth.

Here is a circuit with 0.6V pk-pk input voltage (v_in) for the CE amplifier, 1.17 kHz frequency-
end9.png


For this, without C5 and R9, the AC and DC gain was -10. I was supposed to increase the AC gain to -50 while keeping DC gain intact, so I added C5 and R9 in order to get that. I was supposed to play around with only the emitter leg. It would be nice if someone would confirm if I did it correctly, keeping in mind that frequency for the high pass filter at 3dB is 100 Hz. Also, a lot of non-linearity is observed in the AC gain, which I don' t seem to understand.

The main thing is that, I'm supposed to study the effect of connecting a load impedance from C6 to ground and measuring the output voltage there. Without R10, ##V_{E}## had a peak of 8.8V approx, which is justified by the quiescent collector current, but why did the voltage after C6 drop to around 4.9V? I can't seem to find out. Also, according to me, R10 creates a voltage divider bias, thus ##V_{E}## should be thus 8.8 * 4.7/9.4, which is roughly 4.4 V. Surprisingly, the simulation gives me a peak of about 6.5V for ##V_{E}##, and the voltage measured between C6 and R10 gives me around 2.4 V. This is supposed to be a voltage divider, since I observed that when R10 is very high, normalcy is retained. But, how to calculate these voltages using appropriate equations, as my calculations don't comply with the simulation's?
 
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Someone please atleast give me some insight as to why does ##V_{E}## differ from ##V_{out}##, when the load impedance isn't connected, and how to calculate the voltage divider bias when the load impedance is connected. My calculations don't seem to match with the simulation results.
 
I think you mentioned that you were going to upload your simulation results? (at least PDF screenshots)...
 
berkeman said:
I think you mentioned that you were going to upload your simulation results? (at least PDF screenshots)...
Yeah sure. By the way, I have realized it now, after drawing the AC model, where ##R_{L}## appears in parallel with the collector resistance. I would upload the results once I'm free :)
 
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PhysicsTruth said:
Someone please atleast give me some insight as to why does VE differ from Vout, when the load impedance isn't connected, and how to calculate the voltage divider bias when the load impedance is connected. My calculations don't seem to match with the simulation results.
It looks like LTspice. Can you please upload your file.asc as a text file.
Rename it as file.asc.txt so it can be attached to your next post.
We can then run the simulation and do the numbers.
 
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It is impossible to read the diagram so we need the file.asc
The load resistor looks like it has a value of R10 = 1m = 1 milliohm.
Maybe you intended R10 = 1MEG.
 
Baluncore said:
It is impossible to read the diagram so we need the file.asc
The load resistor looks like it has a value of R10 = 1m = 1 milliohm.
Maybe you intended R10 = 1MEG.
Yeah, 1 mega ohm
 
Did changing that fix the problem?
 

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