Logic Design for Unpredictable Behavior

[kal22]

I have a design issue. I've programmed a CPLD so that it controls whether a MIC can activate or not. There are 8 MICs. A MIC is allowed to activate if there are no opens nor shorts on its lines. Each MIC has 4 wires (red, black, white, green). The red and black wires are for the "push-to-talk (PTT) active" signal. The white and green wires are for the MIC supervision signal. Here's the problem: When a MIC is keyed, the wires are shorted inside the MIC. There's a race between the PTT active signal going through (so that the MIC can activate) and the MIC supervision signal (which detects a short and doesn't allow the MIC to activate, even though it's not a real short on the line). The PTT active signal can go through depending on how fast the MIC is keyed. If the MIC is keyed fast enough, the PTT active signal goes through. If the MIC is keyed a bit slower (meaning the PTT button is pressed slowly), then the MIC short signal goes through and prevents activation when it shouldn't. So my question is... How can I program my CPLD to meet these design requirements, when the speed at which the MIC will be keyed is unpredictable?

 

[berkeman]

I don't understand the design requirement. Since the shorting of the PTT wires is normal operation, why would the CPLD be programmed to detect a short on these lines as a fault?