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Homework Help: Logic gates, inverting output without increasing transistor count

  1. Feb 1, 2012 #1
    1. The problem statement, all variables and given/known data
    Hello all,
    I have the following logic gates:
    (A'.(B+C))' which I had reduced to A+B'.C'. I then want use a NAND gate connected to a NOR gate, then connected to an inverted. However, I have been informed that I need not to use ten transistors, and that 8 can get the job done. How exactly can I invert the output after the NOR gate without the addition of new transistors?
  2. jcsd
  3. Feb 3, 2012 #2


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    Staff: Mentor

    Can you use an OR gate instead of NOR + NOT?

    Otherwise, draw the arrangement you propose using, and you may be able to spot where you can economize on the number of gates.

    B'.C' can be converted to a NOR
    Last edited: Feb 3, 2012
  4. Feb 3, 2012 #3
    Thanks, I managed to get it. It was a lot more simple upon developing and then utilizing a truth table.
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