Master-Slave Flip-Flop Avoids Race-Around Condition

[ranju]

I was studying about the race-around condition , to avoid this condition we increase the propagation delay betond the pulse width but this is a negative thing , I mean increasing the loop or propagation delay is not a good characteristic , generally we try to decrease it but here we are trying to increase it..!
And also we use master-slave flip-flop to avoid race-around condition but I didn't get how it is avoiding race-around condition , even if the master & slave flip-flop works independently on negative & positive edge of the input pulse?? Please explain this...!

 

[sophiecentaur]

I thought the whole point of using what I always knew as synchronous logic, was that logic element used the same edge of the clock pulses. As long as the operational delays of each element are less than a clock cycle, 'race round' problems can be designed out.

 

[Hesch]

also we use master-slave flip-flop to avoid race-around condition but I didn't get how it is avoiding race-around condition

A race condition occurs in sequential logic, as the output from some logic part of the circuit depends on external inputs and its own output ( that is fed back ), thereby making a loop. This race condition can be eliminated by blocking the loop somewhere (the loop is no longer closed). By inserting a master-slave FF somewhere in the loop, the loop is at anytime open as the FF is synchronous and controlled by a clock-signal. E.g. then master latches its input at a positive edge in the clk-signal, and the slave latches the output of the master at the negative edge. Thus at any time the loop is blocked.

A race condition means that the behaviour of the circuit depends on which signal arrives as the first to some inputs. Inserting a master-slave FF secures that all signals arrive at the same time (clocked), ready to be evaluated for a decision: What to do now?

http://www.electronics-tutorials.ws/sequential/seq_2.html

Also race condition in asynchronous sequential logic can be avoided by splitting at sequential complicated step into more simpler steps, each smaller step looking at only one condition at a time, starting with the most important condition (top of some hierarchy).

 

[cnh1995]

I don't know about the propagation delay but as per my knowledge, the slave operates on inverted clock of the master.Thus, when the master is active, slave is inactive and vise versa. The master-slave I've studied is JK-SR flip flop. Race around occurs in JK flip flop when j=1 and k=1 and enable i/p=1. This leads to fast toggling of Q and Q^-..If edge triggering is used, this problem is solved...But a master-slave can work on level triggering..The changed inputs of master (JK) are not fed back immediately to the inputs..So multiple toggling is avoided..This might be the propagation delay you are referring to..The outputs of master are fed back to its inputs after a delay of entire 1 clock pulse..So, edge triggering the JK flip flop or using master slave are the ways to avoid the multiple toggling...You'll see a systematic toggling is obtained in the counters using a T flip flop (shorted JK)..

 

[meBigGuy]

A master slave flip flop is actually a master latch and a slave latch. For a positive edge FF, the master latch follows its input when the clock is low, and the slave latch follows the master when the clock is high.This creates the appearance of a positive edge flip-flop.

If you have logical feedback in a circuit from output to input, and you are trying to create storage with a single latch within the circuit, the latch is combinatorial (transparent) for the duration of the pulse on the gate. During the time the latch is transparent the circuit can feed back. If you replace the single stage latch with a master/slave, then the combinatorial path is always blocked since either the master or the slave are always "closed".

Of course a poorly designed flip-flop can also have feedback problems in that it might fail hold time through the combinatorial paths. But that is a slightly different issue.