Understanding MOSFET Logic Gates: Source, Drain & Ground

[mtanti]

I'm doing logic gates using their basic components MOSFETs. I have no idea how to understand which is the source and drain of the transistor from a symbol diagram when given both the n type and the p type. I also cannot understand what happens when the source is connected to ground. Can someone please explain?
Thanks!

 

[PMASwork]

I did a quick Google search - this should answer your symbol questions:

http://www.tpub.com/content/neets/14179/css/14179_158.htm

The source is sometimes connected to ground because grounds are sometimes used as a current return. Also, in a logic circuit, "ground" is the default "0" by convention.

 

[mtanti]

I'm afraid it doesn't. We didn't use the substrait connection. Our diagram was something like this:

-|[

and one of the legs of the square bracket would have an arrow either pointed to it or away from it. The single connection at the front is the gate whilst the other two on the right are the source and drain.

 

[antonantal]

The "leg" with the arrow is the source terminal. The arrow tells you with what type of MOS you are dealing with by showing you the direction of the voltage between G and S when the transistor is forward biased.

You connect the source to the ground in the case of nMOS which needs a positive voltage between G and S to switch on, so what you do is connect S to gnd and apply a positive potential to G.

 

[mtanti]

ok so the source is always on the arrowed leg and if the arrow points into the mosfet then it is n type meaning that the drain gives current only when the voltage at the gate is greater than the voltage at the source whilst when the arrow points outward it is the opposite. When connected to Vdd, the voltage is considered 1 whilst when connected to ground the voltage is considered 0. Is all this correct?

 

[antonantal]

if the arrow points into the mosfet then it is n type meaning that the drain gives current only when the voltage at the gate is greater than the voltage at the source whilst when the arrow points outward it is the opposite.

No. A voltage arrow points from the higher potential to the lower potential so when the arrow points towards the transistor (i.e. towards the gate) it means that the source has the higher potential meaning it's a pMOS (you know that in order for the p channel to form you got to have the higher potential on the source and the lower potential on the gate, so that the holes will be attracted towards the gate and the electrons rejected from the gate thus forming the channel).

When connected to Vdd, the voltage is considered 1 whilst when connected to ground the voltage is considered 0.

That's right.

 

[chroot]

Uhh.. this thread is pretty scatter-brained.

mtanti, which symbols are you using for your devices? In industry, most people don't use symbols with arrows, since, physically, the MOSFET is symmetric.

The only definite way to tell drain from source for a MOSFET is this:

For an n-channel device, the source is at lower potential. For a p-channel device, the source is at the higher potential.

Note that the word "source" means the terminal from which carriers are supplied. An n-channel device uses electrons for carriers, and electrons come from the terminal with lower potential. A p-channel device uses holes for carriers, and holes from the terminal with higher potential.

This rule always works, no matter what the symbol looks like, or which leg the arrow's on, etc.

- Warren

 

[antonantal]

mtanti, which symbols are you using for your devices? In industry, most people don't use symbols with arrows, since, physically, the MOSFET is symmetric.

Yes but some universities use this convention. The Sedra & Smith textbook also does. As I said it's an arrow on the source terminal, just like on the emitter of a BJT, only now it indicates the direction of the voltage between gate and source when the MOSFET conducts, thus telling you what type of MOS you are dealling with, based on the same principle that you described. I think it's pretty useful because when you're given a scheme you can see faster if the MOS conducts or not by comparing the direction of the arrow with the direction of the actual voltage on the particular circuit.

 

[chroot]

I think it's pretty useful because when you're given a scheme you can see faster if the MOS conducts or not by comparing the direction of the arrow with the direction of the actual voltage on the particular circuit.

An NMOS device conducts when its gate is Vt above its source. A PMOS conducts when its gate is Vt below its source. You don't need the arrows to figure out when a device is on. The arrows add nothing but extra stuff for students to get wrong.

- Warren

 

[antonantal]

An NMOS device conducts when its gate is Vt above its source. A PMOS conducts when its gate is Vt below its source. You don't need the arrows to figure out when a device is on. The arrows add nothing but extra stuff for students to get wrong.

- Warren

I don't think I ever had to use the threshold voltage in a digital circuit problem to find out if a MOSFET conducts or not. Most of the times I just looked at the direction of the voltages. Anyway, it's true that you don't really need the arrow on the MOSFET in a digital circuit. But in an analog circuit I can't see how you could tell the difference between a nMOS in linear regime and a pMOS in cutoff regime if you use the same symbol for both.

 

[chroot]

Well, the exact same symbol is never used for both; either the PMOS has a circle on its gate, or you use the arrow notation. I'm not saying the arrows have no meaning (they can distinguish n-channel and p-channel devices), but they do not actually determine which terminal is the source or drain. The only way to determine that is the look at the voltages on those terminals, as compared to the gate.

It is absolutely not correct to say that the leg with the arrow is the source, even though, admittedly, this "rule of thumb" will be true in probably 99% of digital designs and 90% of analog designs.

- Warren

 

[antonantal]

...they do not actually determine which terminal is the source or drain. The only way to determine that is the look at the voltages on those terminals, as compared to the gate.

I agree with this

 

[es1]

VLSI designers often don't use the symbol with arrows but board designers almost always do. This is because those devices are not symmetric. The source is often shorted to the base inside the package (Which, in fact, is what the extra leg with the arrow leading to the source is telling you. That the base and source are shorted. Unfortunately many board designers don't want to draw one extra line so they just put the arrow on the source.) and the source is usualy given extra pins so that the voltage at the source inside the package is similar to the voltage on the outside (more parallel paths, less resistance, less voltage difference when Ids>0).
Then there are other things that most board FETs have integrated, like esd diodes, that make the symbol not symmetrical. But this is more due to bad conventions of not including them in the symbol than the direction of the arrow and it showing you the source.

 

[chroot]

es1,

The OP was talking about logic gates -- and you're not going to design those with monolithic, discrete MOSFETs.

Besides, the datasheet for every such MOSFET should explicity show the substrate connection (if any exists), and ESD structures and other integrated components.

- Warren

 

[mtanti]

Guys please, I'm seeing an OR gate in front of me which I'm concluding it will always let a voltage out and a NOT gate which always gives out a 1... Could you post something more helpful on how mosfets operate coz my lecturer just isn't helping enough...

 

[chroot]

The inverter is the simplest CMOS gate. It has an NMOS on the bottom and a PMOS on the top.

When the input is a one, the NMOS is turned on (because its gate is higher than its source), and the output is pulled to ground. The source of the NMOS is the terminal tied to ground. The PMOS, on the other hand, is turned off.

When the input is a zero, the PMOS is turned on (because its gate is lower than its source), and the output is pulled to VDD. The source of the PMOS is the terminal tied to VDD. The NMOS, on the other hand, is turned off.

That's all there is to a CMOS inverter. Does that help?

- Warren

 

[mtanti]

lets try digesting things a bit...
the leg with the arrow is the supply
let D=drain, G=gate, S=supply
if the arrow points inside the mosfet D=1 when G<S (G=0,S=1)
if the arrow points outside the mosfet D=1 when G>S (G=1,S=0)

is this ok? because if the first is true then in a NOT gate the supply of the p type (thats what is written in my notes) is the ground which doesn't make much sense to supply a component with 0 volts...

 

[chroot]

Yikes, you are overthinking this enormously. First, I really think your life will be easier if you learn to disregard the arrows. As I have said, I feel they are nothing more than useless decoration to give students something to get wrong on tests.

The MOSFET, as used in integrated circuits, is normally a symmetric device. There is absolutely no difference between the source and the drain (don't call the source the "supply," as that's horribly misleading).

The only piece of information that you should gain from the arrows is whether a device is PMOS or NMOS. Of course, in CMOS circuits, this is very easy to tell just by their positions.

If you look at, for example, the NMOS device on the bottom of the inverter, you'll see that one of its terminals is connected to ground. The other is connected to the gate's output. This means that the terminal connected to ground is always at a lower potential than the other, and, I've said, that's the definition of an NMOS's source. For an NMOS, the source is always the terminal with lowest potential.

When the gate of the NMOS is more than a threshold voltage above it's source (ground), the NMOS conducts, and pulls the output to ground.

The opposite happens with the PMOS. Its source is the terminal with highest potential -- the one connected to VDD. The PMOS turns on when its gate is more than one threshold voltage below its source (VDD), and it pulls the output to VDD.

- Warren

 

[rockstar]

why would you be using mosfets for logic gates, correct me if I'm wrong but aren't they generally used for power handling

 

[Maxwell]

why would you be using mosfets for logic gates, correct me if I'm wrong but aren't they generally used for power handling

Absolutely not. CMOS logic gates are very common.

 

[chroot]

Actually essentially every digital circuit designed today uses CMOS MOSFETs.

- Warren

 

[Maxwell]

chroot -- is Cadence Virtuoso/Schematics the design tool of choice in industry? I just took a CMOS design class where we used Virtuoso with HSpice and AvanWaves, and I felt that designing larger circuits was sort of tedious. However, I assume that you don't start a new design on the layout level in industry. Do you have a set of cells that you use over and over in your designs, or do you design new cells from scratch for each project? How do you break up a project into pieces considering each person has a different style of design?

Edit -- Also, how many metal layers are generally used in modern designs?

 

[chroot]

Well, no one designs digital logic by hand anymore. You don't design logic with schematics, you use Verilog or VHDL, and then synthesize that into a gate-level netlist. Then you pass it though a place-and-route tool, and out pops your layout.

- Warren

 

[Maxwell]

Ah, that makes sense. I recently did a layout for a 16-bit adder and it was quite possibly one of the most tedious things I have ever done.

 

[chroot]

There are libraries upon libraries of building-blocks like adders, and, in fact, it takes a lot of wizardry to design and lay out a really good one. No one in their right mind actually reinvents that wheel.

- Warren

 

[Maxwell]

Good to hear.