Multiphase clock generator circuit and control logic

[Nabeel]

I want to design a multiphase clock generator circuit and control logic. The circuit will have a 250 MHz clock and the circuit will generate three non-overlapping clock phrases running at 50 MHz. Each clock phase has an associated output driver that can drive up to a 10pF load with no more than a 0.6 nanosecond rise/fall time. The clock generator circuit has a "sleep" mode (all the outputs go to low and stay there) that is initiated one clock cycle after the input A,B and C make the following expression true:
F=A*B+NOT(A)*B*NOT(C)+NOT(B)
When this happens all outputs go low, a confirmation signal (Co) goes high,and the outputs stay low until F turns false.

Please guide what circuits can I use to implement this idea.

 

[Baluncore]

Do the phases need to be of the same duty cycle ?
I have a question about how you get three states at 50 MHz from a 250 MHz master clock.

If you have 3 phases and 3 spaces then that is 6 states. 250 / 6 = 41.666 MHz, not 50 MHz.

If you have 3 phases with delay to prevent overlap you get 250 MHz / 3 = 83.333 MHz.

 

[Nabeel]

No, the phases don't have to be of the same duty cycle.

What I thought of the circuit is that it should have a three phase clock generator,the function,the frequency divider,zero clock T gate & the D flip flop.

 

[berkeman]

I want to design a multiphase clock generator circuit and control logic. The circuit will have a 250 MHz clock and the circuit will generate three non-overlapping clock phrases running at 50 MHz. Each clock phase has an associated output driver that can drive up to a 10pF load with no more than a 0.6 nanosecond rise/fall time. The clock generator circuit has a "sleep" mode (all the outputs go to low and stay there) that is initiated one clock cycle after the input A,B and C make the following expression true:
F=A*B+NOT(A)*B*NOT(C)+NOT(B)
When this happens all outputs go low, a confirmation signal (Co) goes high,and the outputs stay low until F turns false.

Please guide what circuits can I use to implement this idea.

No, the phases don't have to be of the same duty cycle.

What I thought of the circuit is that it should have a three phase clock generator,the function,the frequency divider,zero clock T gate & the D flip flop.

Since this is your schoolwork problem, you need to show a fair amount of initial effort, before we can be of tutorial help. Can you show us some techniques that can be used for this problem?

 

[Nabeel]

My work

I will add information for what I have worked with the solutions and the diagrams below:

This is the logic diagram and CMOS schematic diagram of the Non-overlapping clock signals.

I want to input a spice code which will run my design and output three non-overlapping signals at p1,p2 and p3

The following is the function created which will be inputted into the clock generator.

My question is that there will be 250MHz clock input but as the questions says. The clock generates three non-overlapping clock phases running at 50MHz. Which means I have divide the three phases from the

.

 

[Nabeel]

The Question says the the circuit makes use of a basic 250 Mhz clock. Using this clock the circuit generates three non-overlapping clock phases running at 50 MHz. Does this mean I only have to use 50MHz from the Master Clock?

 

[berkeman]

Can you say more about the difference between overlapping and non-overlapping clock signals?

 

[Nabeel]

In one of the previous assignments I have made a non-overlapping circuit

and the resulting waveform was achieved.

From this circuit and waveforms it can easily be seen that on any given instance, only one of the clock of PHI is high and the other is low and vice versa

Overlapping would simply mean that both of the output PHI's are high at the same time.

It should also be noted that PHI1 will occur first then PHI2 and same principle would apply for PHI3

 

[Baluncore]

Does this mean I only have to use 50MHz from the Master Clock?

No. It probably says not to use a VCO and PLL with two dividers to synthesise 300 MHz.

Whatever you do there must be a fundamental frequency division by a factor of 5 somewhere.
If you use a ring counter to do that division you will get 5 output phases. How many did the question say you needed? How many will you use?

You can use the phase of the input signal to prevent overlap of the output pulses.
With a 5 bit ring counter that may give you up to 10 “time slots”.
You might allocate slots 1 and 2 to first phase, 4 and 5 to second phase, 8 and 9 to third phase.
The phases would be all the same duty cycle, the gaps would be variable.

There must be possible a simple walking-ring state-machine that generates three non-overlapping phases when clocked at 250 MHz. It can do that by advancing some stages on the positive clock edge and some on the negative edge. It will have from 5 to 10 distinct states. You will use three of those states for your phase outputs.

Now you only have to design it.

 

[berkeman]

In one of the previous assignments I have made a non-overlapping circuit View attachment 69572 and the resulting waveform was achieved.

From this circuit and waveforms it can easily be seen that on any given instance, only one of the clock of PHI is high and the other is low and vice versa

Overlapping would simply mean that both of the output PHI's are high at the same time.

It should also be noted that PHI1 will occur first then PHI2 and same principle would apply for PHI3

I'm having trouble understanding the question (not your fault). Clocks being high or low does not matter in the real world of circuit design. What matters is where the edges of the clocks are -- clock edges are when things change in synchronous circuits. So whether a clock is high or low does not matter, what matters is the timing relationship between edges.

Can you say more about what you have learned about overlapping and non-overlapping clock levels? Why does that matter?