I want to design a multiphase clock generator circuit and control logic. The circuit will have a 250 MHz clock and the circuit will generate three non-overlapping clock phrases running at 50 MHz. Each clock phase has an associated output driver that can drive up to a 10pF load with no more than a 0.6 nanosecond rise/fall time. The clock generator circuit has a "sleep" mode (all the outputs go to low and stay there) that is initiated one clock cycle after the input A,B and C make the following expression true: F=A*B+NOT(A)*B*NOT(C)+NOT(B) When this happens all outputs go low, a confirmation signal (Co) goes high,and the outputs stay low until F turns false. Please guide what circuits can I use to implement this idea.