Need a voltage divider for a capacitor source voltage

[imsmooth]

My goals is to get a good zero crossing trace for my capacitor voltage. I was able to get a good noise-free signal with an optocoupler I had lying around. The violet trace is the output when analyzing the capacitor voltage (not shown on the scope).

The problem is that I need a resistor to limit the maximum current to the LED to 25ma, which increases the voltage necessary to get the coupler to start detecting a lower voltage.

I'm trying to go through the data sheets on mouser and digikey to find one that has fast switching, low turn-on voltage, minimal propagation delay and a diode that can tolerate a higher current to give me the ability to detect a voltage ranging from 0-500Vrms.

Any suggestions for a good optocoupler/isolator?

 

[Baluncore]

My goals is to get a good zero crossing trace for my capacitor voltage.

Why, or what will you use the signal for?
You need to write some specifications. How do you define "good" ?

An optocoupler and resistor is not the solution if you want a crisp edge at the right time. An optocoupler will always switch a few volts late, while resistor current will be lowest, just when you need it to be greatest, and greatest when you want it to be lowest.

There are many solutions, each with its own pros and cons.

It seems you do not want a pulse on crossing, but a square wave that is in phase with capacitor polarity. How close to in phase?
Do you require symmetry, or can the wave have a fast rising edge with a slower falling edge?

 

[TonyStewart]

You must learn to define acceptance criteria.

https://tinyurl.com/2qt2ee2r

 

[imsmooth]

I just seem to go deeper into the rabbit hole.

Baluncore, you are right. I don't want pulses on zero crossing, but a square wave that closely matches the polarity of the capacitor, Symmetry would be preferred.

Tony, the Falstad applet was really nice. I'm sure much of what I think is wrong so I am ready hear the right answer:

I thought the purpose of the isolator was so two dissimilar circuits could get "linked". The diode simply needs current from a closed loop to turn the other side on and off. Why does the left side of the circuit need to share a ground? Can't I run the left side with a non-grounded, floating sinusoidal voltage source?

Also,
1. What's the purpose of the schottky diode? When I delete it nothing seems to change.
2. What is the purpose of the 1M on top of the 100pF capacitor in parallel? You have capacitance 100:1 divider.How are you are picking the value of the resistor to go with the 100p capacitor?

 

[TonyStewart]

The 100 pF was a current limiter voltage divider. The 1Meg and clamp diode were redundant for a unipolar signal 0 top 400V.

now I AC coupled reduced current to <4mA and phase shifted diode current 90 deg. The 10k senses current limited by the C reactance with some tiny fringe effects on duty cycle.

duty cycle is 50% +/-2 https://tinyurl.com/2pyrb6a2

 

[imsmooth]

In both of your applets will the isolator's diode work when the AC source voltage is very low? I see it works on the simulation. The issue I was having was at low voltages there was not enough current to turn the isolator's diode on.

Also, the phase error addition aside, what is the functional difference between the two applet's output?

 

[TonyStewart]

When input current is low, you raise collector R value the same and buffer as I did. The diodes capacitance is not modelled so there are freq. limits and also tolerances on hFE are not an option there.

Often the opto losses are near the hFE gain so you see the CTR specs. are near 1 or worst case maybe 10% and best case >> 100% but the biggest variable in production is hFE. (depending on p/n)

 

[Baluncore]

The diode, in antiparallel with the optocoupler LED, prevents destruction of the LED by reverse voltage.

The greatest slew-rate of the capacitor voltage is at the time of the zero-crossing. It would be sensible to use a capacitor to deliver the current needed to drive the optocoupler LED. The gating of that current through the optocoupler could be done by the capacitor voltage.

 

[TonyStewart]

The gating of that current through the optocoupler could be done by the capacitor voltage.

meaning:
Since I chose a small series C , its impedance being highest by far the 90 deg. Phase shift is dominated by Vc drop and < 1% by load= Vf/If +Rs, so the phase error is low.

Since the largest voltage drop is across C and current sensed by the real R (albeit nonlinear diode effect, it is still real R. for the most part neglecting low current diode capacitance)

In the initial divider we had matched R1C1 to R2C2 to get a wide spectrum voltage divider rather than the familiar partial derivative frequency response.

 

[imsmooth]

When input current is low, you raise collector R value the same and buffer as I did. The diodes capacitance is not modelled so there are freq. limits and also tolerances on hFE are not an option there.

You're referring to the 10k resistor as the current sense, right?. If the voltage goes up on the cathode side of the LED diode doesn't that decrease the voltage drop across the diode and hence the current driving it? When you say "raise" the collector R are you saying you choose different design values? My issue is the voltage source varies from 0 to 500Vrms and the value of R would be fixed.

 

[imsmooth]

The diode, in antiparallel with the optocoupler LED, prevents destruction of the LED by reverse voltage.

Would any hyperfast Schottky diode work?

 

[Baluncore]

Please do not edit inside a quote, because then we can't quote your post.
Click on the [ ] button to toggle BB code.

Would any hyperfast Schottky diode work?

Any diode would work. It only has to conduct the LED current, or withstanding a couple of LED forward volts.

 

[berkeman]

Please do not edit inside a quote, because then we can't quote your post.
Click on the [ ] button to toggle BB code.

(I fixed up the quote box, and sent him a PM about it)

 

[imsmooth]

meaning:
Since I chose a small series C , its impedance being highest by far the 90 deg. Phase shift is dominated by Vc drop and < 1% by load= Vf/If +Rs, so the phase error is low.

Since the largest voltage drop is across C and current sensed by the real R (albeit nonlinear diode effect, it is still real R. for the most part neglecting low current diode capacitance)

If I understand the model correctly, the series capacitor (and resistor) is limiting the current to a safe level for the optoisolator when the voltage is near the maximum. What happens when the voltage is near the minimum? There will not be enough current to drive the LED, right? If this is correct, is there anything that can be done so the circuit works over most of the input voltage range?

 

[TonyStewart]

You're referring to the 10k resistor as the current sense, right?. If the voltage goes up on the cathode side of the LED diode doesn't that decrease the voltage drop across the diode and hence the current driving it? When you say "raise" the collector R are you saying you choose different design values? My issue is the voltage source varies from 0 to 500Vrms and the value of R would be fixed.

Yes 10K does limit the peak current over a small range only.

You will never be able to detect a signal over a 40 dB dynamic range, unless you use AGC or an active current limiter. The opto is not the best choice for a dynamic input signal. Often these are done with PLL's and lock-in amplifiers or precision comparators with a high SNR signal and a wide CM in put range using the RC divider.
You need a high speed linear opto to saturate an open collector at 75 kHz at low output current, perhaps the 6N136 but with 47 k to 5V that is only Ic < 100 uA so with 10% CTR you need 1mA input.

So I would not recommend this approach if you are hunting for resonance and have no output. I would use an automatic hardware based linear resonant oscillator method that oscillates from phase of the attenuated output for AC feedback or a PLL.

 

[Baluncore]

@imsmooth10
If you need a zero-crossing detector to help auto-tune your generator and tank, you might consider two identical attenuators and a mixer or multiplier, followed by a low-pass filter. That makes a phase detector. If you multiply the drive voltage by the capacitor voltage, the average DC output from the LPF will be zero when tuned. The LPF output voltage passes through zero as the drive frequency crosses the LC resonant frequency. The detected voltage can be used to drive a motor, or software, to tune the drive or the tank.

 

[TonyStewart]

@imsmooth10
the average DC output from the LPF will be zero when tuned.( in a PLL)

Generally, the DC output in a linear phase mixer is 50% of the 180 degree output swing for the polarity that causes negative feedback. This may lock if the difference frequency is within the "capture range" of the PLL. The range of 180 to 360 degrees has the opposite triangle slope, causing positive-feedback, which pushes the VCO away. When capturing the time spent in positive feedback is push fast, so when negative it slows down and the average effect is to pull towards the same frequency and at 90 deg with DC and a 2f output. When outside the capture range, the feedback time is balanced for each phase, and it does not lock. The capture range is determined by the LPF BW and the VCO error f and loop gain with phase compensation filter. The mixers typically used are XOR gates, so the lock-in voltage is Vdd/2 using the CD4046 or equiv.

https://web.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf

 

[Baluncore]

The mixers typically used are XOR gates, so the lock-in voltage is Vdd/2 using the CD4046 or equiv.

I do not suggest nor recommend an XOR gate, as that would be biased by the logic rail voltage and would require some form of voltage comparator on both inputs. My aim was to escape from the need for a comparator and the delay of the requisite high gain digital path.

The phase detection should be based on the amplitude of the sinewave over the period, rather than just the time of two switching edges from some hysterical quantifying logic.

That is why I suggested using an AC coupled analogue multiplier, an MC1496 Gilbert cell, or possibly an RF mixer. The output would be symmetrical about zero, so would be signal-gain and supply-voltage independent.

The phase of the lock of a PLL is quite irrelevant to the analogue solution. It is trivial to swap the differential inputs of an analogue multiplier, to compensate for an inverting miller-integrator in the LPF.

 

[TonyStewart]

I do not suggest nor recommend an XOR gate, as that would be biased by the logic rail voltage and would require some form of voltage comparator on both inputs. My aim was to escape from the need for a comparator and the delay of the requisite high gain digital path.

The phase detection should be based on the amplitude of the sinewave over the period, rather than just the time of two switching edges from some hysterical quantifying logic.

Facts from datasheets.
- The XOR gates may be capable of similar BW of Gilbert Cell useful for << 10MHz output.
- XOR gates do not introduce hysteresis and in quadrature are low noise and linear.
- PLL chips just use very high GBW of self-biased CMOS limiters
- single IC PLL's provide simplicity if tolerances are adequate.

 

[Baluncore]

Facts from datasheets.

Please identify the datasheets that make those statements, that you claim to be fact.

- The XOR gates may be capable of similar BW of Gilbert Cell useful for << 10MHz output.

An XOR is digital, a Gilbert cell is analogue, Gilbert cells work well at VHF frequencies.

- XOR gates do not introduce hysteresis and in quadrature are low noise and linear.

Voltage comparators introduce hysteresis.
How can an XOR logic gate be linear, z = a*(1-b)+b*(1-a) ?

- PLL chips just use very high GBW of self-biased CMOS limiters

I agree, they use self-biased CMOS inverting amplifier chains, to get within one volt of the supply rails, and then they revert to logic gates, inherently based on the time of the transitions.

- single IC PLL's provide simplicity if tolerances are adequate.

Anything is acceptable if you lower the requirements sufficiently. A marketing platitude, and a truism.

 

[TonyStewart]

Please identify the datasheets that make those statements, that you claim to be fact.

An XOR is digital, a Gilbert cell is analogue, Gilbert cells work well at VHF frequencies.

The output does not respond to VHF only HF. The input may be VHF.

The phase detector response of the XOR gate does not follow your logic.

Voltage comparators introduce hysteresis.
How can an XOR logic gate be linear, z = a*(1-b)+b*(1-a) ?I

p7 shows DC to 50 MHz in this family . Many are more and less https://www.ti.com/lit/gpn/sn74hcs86

The way XOR gates and Gilbert multipliers alike work as linear phase detectors is to produce a pulsewidth in quadrature phase-lock proportional to the linear phase difference. The advantage of Gilbert cells only occurs from increase dynamic range for linear amplitude multiplier output not linear phase, but thus shows better results for RF analog demodulators, not used here.

The old Motorola multiplier IC has a known self-resonant frequency at 10MHz that must be avoided on the output.

 

[Baluncore]

The phase detector response of the XOR gate does not follow your logic.

Can you be more specific, which logic does it not follow?

 

[TonyStewart]

Which logic is that?

Voltage comparators introduce hysteresis.
How can an XOR logic gate be linear, z = a*(1-b)+b*(1-a) ?

See f(A) XOR f(B) has no hysteresis

https://www.qsl.net/w/w2aew//youtube/Basics_of_PLLs.pdf

 

[Baluncore]

See f(A) XOR f(B) has no hysteresis

An XOR gate is not a voltage comparator, so obviously it needs no hysteresis.
Ignoring hysteresis, the XOR is still non-linear. z = a*(1-b)+b*(1-a).
That is why it can be used as a mixer, or as a direct-sequence modulator.

 

[TonyStewart]

Respectfully, I have designed dozens of different PLL's in my career so I am quite familiar with all the characteristics and terminology. So to avoid further non-sequiturs, let me explain again. PLL's for tuning a tank circuit to resonance can be quite simple, with no need for a uC or a Gilbert Multiplier. The sine waves may be turned into logic levels with or without hysteresis if the benefit is to eliminate redundant transitions, which only reduces the gain of the loop in this very short transition.

Yet this is irrelevant as the operating point of "the loop" is always furthest away from the transitions to have a balanced DC voltage when integrated results in no change to the tuning of the VCO.

The integration may be done with open collector/drain charge pumps an active integrator, or simply the quasi-integration of a low pass filter on the error signals with sufficient loop gain.

We do not call it a direct-sequence modulator for this task. It is a frequency mixer and after integration or low pass filtering, the result is a phase detector as phase is the integral of frequency regardless of linear or digital amplitude.

 

[Baluncore]

Respectfully, I have designed dozens of different PLL's in my career so I am quite familiar with all the characteristics and terminology.

Then you need to learn that, when you are holding a hammer, everything is not a nail.

So to avoid further non-sequiturs, let me explain again.

We do not call it a direct-sequence modulator for this task.

Of course, we do not. I was NOT discussing PLLs, I was discussing non-linear XOR gates, as used for phase detection, or the simplest modulation application. You seem determined to misinterpret what I write, so you can then smother it in irrelevancy.

The OP wanted a wideband attenuator, without phase shift, to feed a comparator. I have simply pointed out that a multiplier, used as a phase detector, could eliminate the need for the comparator.

The OP has been careful NOT to say why the comparator was needed. You now insist that I must be wrong, because to complete what is clearly an unspecified project, you would use a digital PLL.

 

[TonyStewart]

You are polluting the thread with amplitude "non-linear" criticisms of XOR gates that are irrelevant. The case here is for "linear-phase" not linear multiplying amplitude and phase, which is useful to mix RF signals and may be used here, but is not mandatory. Then your phase error voltage is sinusoidal at the error frequency and not a linear triangle wave with time as with XOR logic which can be implemented much simpler as indicated previously. His end goal was to make the PLL using a uC firmware measuring tank current phase. Your criticisms of my suggestions were invalid, except for requesting reference specs which did support. This should not continue here and be a parking lot discussion.

 

[berkeman]

Thread is closed for Moderation...

 

[berkeman]

This thread will remain closed. The OP has started a new thead to try to re-focus the discussion. I'll be watching that thread closely, so keep the discussion on-point please. Thank you.

https://www.physicsforums.com/threads/help-with-proper-grounding-with-oscilloscope-tracings.1052345/