Normally I would ask this in the HW section but I think this would be better directed towards EE's. I am trying to design a circuit for a design project that will take a 4-bit two's complement number (IE: A3A2A1A0) and output true if it is greater than another 4-bit two's complement number (IE: B3B2B1B0). I can make use of basic gates or full-adders. I am trying to approach it using only basic gates because I would have to deal with overflow issues with full-adders. So what I was thinking is that I could compare the MSB first, and if it is 0 for A and 1 for B, then I know A > B and output 1. If the MSB for A and B are both the same, then I need to look at the next bit over. Here, if the MSB's of A and B were 0, then I would output true if the next bit for A is 1 and B is 0. If the MSB's of A and B were 1, then I would output true if the next bit for A is 0 and B is 1. But then there is the case where the next bit for A and B are both the same, which would mean I have to dig to the next bit. Basically, I am wondering how can I simplify this by not "digging" so deep into the bits and making use of so many gates. IE: I want to use reasonable engineering effort, even though Verilog will simplify it when I go to program on the GAL's, I want the paper design to be efficient. Can anyone suggest a way I can infact use full-adders? We just got into them in lecture and I am still unsure how they work. Thanks!