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New to using a breadboard, little help

  1. Feb 5, 2008 #1
    So Im taking intro to logic and our first lab has to do with implementing equations on a breadboard. I understand the equations and I get how a breadboard works.
    this might be a dumb question but what does it mean to implement an equation on a breadboard? do you wire it up and then make a LED light up or what?

    my three equations I have to implement are:

    f = x'y'z' + x'yz' + xyz + xy'z
    g= x'z' + xz
    h= (x' + z')(x + z')

    how would you put these on a breadboard, like what am i aiming to accomplish? Im supposed to wire each one seperatly and make sure that they all behave the same way.
     
  2. jcsd
  3. Feb 5, 2008 #2

    berkeman

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    You can either use a logic analyzer (or a multi-channel oscilloscope) to demonstrate the IO transfer function, or yes, you could use DIP switches at the inpurs (x,y,z) and LEDs at the outputs (f,g,h) to show identical behavior. You implement those equations on the breadboard using ICs with gates inside them.

    Which ICs are you going to use? What is the voltage of your power supply? What do you think you should do with any unused inputs to your logic gates?
     
  4. Feb 5, 2008 #3
    im to use AND, OR, and NOT gates to construct those equations. I beleive the voltage is 5 volts? but im not sure about the other inputs, i thought i just could leave them unconnected.
     
  5. Feb 5, 2008 #4

    berkeman

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    Nope, tie off any unused inputs either high or low. Quiz question -- how do you tie off unused inputs on the following gates so as to not affect the output of the gate adversely?

    AND gate --

    OR Gate --

    NAND gate --

    NOR gate --
     
  6. Feb 5, 2008 #5
    no idea lol
     
  7. Feb 5, 2008 #6
    I would review "Sum of Products" and "Product of Sums" in your class literature. There should also be a section in the book/notes that show you how to implement these two forms. Remember that an "OR" gate is represented by addition and that an "AND" gate is represented by multiplication.
     
  8. Feb 5, 2008 #7
    That is a very good question...(to one I don't think I know if my answer is correct or not) This reminds me why I see unused parts of the chip still connected to something on schematics.
     
  9. Feb 6, 2008 #8
    typically just tie the input to gnd and let the output float, at least that is what i do if i'm not using that pin. if its an AND gate then to high so you can toggle the other input to make the output high or low.
     
  10. Feb 6, 2008 #9

    berkeman

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    Correct. Because:

    x AND 1 = x

    x OR 0 = x
     
  11. Feb 6, 2008 #10
    berkeman, were you the one who said on this forum before that if you let the inputs float. This could confuse the gate and cause noise voltage to appear at the output of used gates.
     
  12. Feb 6, 2008 #11
    thanks guys, i think i actually get it now. i put this thing together tomorrow in my lab so hopefully i get it. thanks for your help!
     
  13. Feb 7, 2008 #12

    NoTime

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    That's correct.
    How big a problem this is depends on the exact logic family being used.
    It is a very important consideration for cmos parts.
     
  14. Feb 7, 2008 #13

    berkeman

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    The two big problems with floating CMOS inputs is noise (the gate can buzz as the inputs float around between high and low), and increased Idd when the gate input floats near mid-supply (turning on both the pullup and pulldown transistors in the input stage). Bad news.
     
  15. Feb 7, 2008 #14
    yo can use the pspice to simulte that equation by drawing those gates. Then, it'll be easy to verify what you got pratically. use some gates and hook them up to a 5v and LEDs ....good luck
     
  16. Feb 8, 2008 #15
    Does this cause the gate to latch up and draw a lot of current? Or just causes the signals are the used outputs to be noisy?
     
  17. Feb 8, 2008 #16

    berkeman

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    No latchup, just noise and extra (and variable) Idd. To get SCR latchup, the input needs to be driven outside of the rails (like above 5V or below GND) by a diode drop or more, and the source for that drive needs to be able to supply the minimum latchup gate current. When you do get SCR latchup, though, that turns on a low impedance between Vdd and GND, and can fry the chip.
     
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