PCB Layout questions for my High Voltage circuit

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Discussion Overview

The discussion revolves around the design considerations for a high voltage circuit involving 2 kV film box capacitors used in series across a 4 kV power supply. Participants explore issues related to component spacing, voltage ratings, insulation, and safety in PCB layout for high voltage applications.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Conceptual clarification

Main Points Raised

  • One participant questions whether the clearance between the 2 kV and 4 kV pins needs to be at least 10 mm, given that each capacitor is rated for 2 kV but could see 4 kV with respect to ground.
  • Another participant suggests that the voltages across the capacitors may differ due to charging, transients, and parasitic effects.
  • Concerns are raised about the tracking of high voltage across a PCB, with a recommendation to use a separate PCB for high voltage components.
  • Participants discuss the importance of using balancing resistors in parallel with capacitors to ensure even voltage sharing, with suggested resistance values between 1 Meg and 10 Meg.
  • One participant highlights the failure modes of film versus ceramic capacitors, noting that film capacitors typically fail open while ceramics may fail short.
  • There is a discussion about the implications of capacitor case insulation and whether the potential difference between the cases should be considered in design.
  • A participant emphasizes the need for safety, performance, and reliability in high voltage design, suggesting that manufacturers should provide guidelines for insulation strength.
  • Another participant mentions the importance of understanding creepage versus clearance in high voltage applications.

Areas of Agreement / Disagreement

Participants express various viewpoints on the adequacy of component spacing and the implications of voltage ratings, leading to multiple competing views. The discussion remains unresolved regarding the consideration of potential differences between capacitor cases and the appropriate design practices for high voltage circuits.

Contextual Notes

Participants acknowledge limitations in their understanding of capacitor insulation and the potential for arcing between terminals on the PCB surface. There is also mention of the need for further clarification on specific design guidelines and the differences between creepage and clearance.

js2020
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TL;DR
I am considering what is adequate component spacing
I am looking at using a few 2 kV film box capacitors in series and I'm trying to make the board as compact as reliably possible. Let's say that I have two equal valued series capacitors rated for 2 kV each in series across a 4 kV power supply. Each capacitor will then have a voltage at 2 kV. Using the online calculator at https://www.smps.us/pcbtracespacing.html which is based on IPC-2221, the external spacing for 2 kV is 10 mm. Do I only have to ensure that the clearance between the 2 kV and 4 kV (with respect to ground) pins are at least 10 mm apart? Or should I consider that the capacitor dielectric is only rated for 2 kV and will actually see 4 kV WRT ground?

Since we don't really know what the voltage of the plastic case is, if we consider that it is the worst case for this setup of 2 kV, how do you typically consider the nearby parts and their voltage rating?
 
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js2020 said:
Summary:: I am considering what is adequate component spacing

Lets say that I have two equal valued series capacitors rated for 2 kV each in series across a 4 kV power supply. Each capacitor will then have a voltage at 2 kV.
Not necessarily. Quiz Question -- Why not?
 
They may have different voltages due to charging/transients and parasitics.
 
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Or different capacitance based on the specified tolerance and even lifetime aging effects.
 
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Tracking of HV across a PCB is common. Use a separate PCB for high voltage. Mill slots in the PCB below capacitors and between terminals to reduce tracking.

Be conservative. When calculating the required breakdown voltage of capacitors in series, assume one will be a short circuit, with no voltage. You need n+1 capacitors.

When connecting capacitors in series, place a high resistance in parallel with each capacitor so as to share the voltage evenly. I expect for a few kV that resistance will be between 1 Meg and 10 Meg.

In effect you will have two series voltage dividers, one resistive (DC), the other capacitive (AC), closely connected as a parallel ladder. The only requirement is that all the parallel RC products are about the same.

Normal resistors are only rated to about 150 volt, above that they go open circuit. Look for specified HV resistors, so you need less of them.
 
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Assuming one is short would decrease the power density by >33% as I would have to use 3 x 2 kV capacitors in series. Isn't one of the benefits of film that it actually fails open? I know that traditional ceramics tend to fail short due to stress cracks and moisture ingress (among other contaminants). From my understanding, ceramics have the disadvantage of lower operation temperature but have so called self healing properties...aka the film simply burns in localized spots which of course slightly reduced capacitance.

That's a good point about the balancing resistors. I'm using 6 series 1 MEG 1 W Ohmite HV thick film resistors. The reason for 6 is to limit the power dissipation to about half of their rated power.

I'm still not sure about my original question though. I was wondering about the capacitor's clearance because of the capacitor's insulation. Of course the voltage rating is due to the dielectric making up the capacitance, but what about the plastic case which serves as insulation to outside components? If the voltage rating of the capacitor is 2 kV...I have that capacitor connected to GND and 2 kV. Then I have another series capacitor connected to 2 kV and 4 kV, why would you not also consider that the 4 kV capacitor is near GND when next to the 2 kV cap since there are GND planes within that capacitor. Therefore, it's actually seeing a maximum differential of 4 kV WRT external components. In other words, if I eliminate the potential issue of the terminals and tracking across the PCB, I would have to worry about the insulation between the capacitor shells at some point, right? Is that voltage so high that it's never considered?
 
The reason for an assumed short is not a capacitor internal failure, but an arc between terminals on the PCB surface.

If you place the capacitors end to end the nearest points will all be at the same potential. Those modular “stick capacitors” will have a terminal at each end. Don't forget the parallel resistor chain shares those equipotentials.

I once repaired an Atomic Absorption Spectrometer that had CMOS logic, analog gates and EHT, all on one big PCB. The circuits were more interleaved than well separated. Once the EHT escaped it took out all sorts of random gates. Dust and moisture had built up until it went bang. I built a new separate PCB for the EHT voltage multiplier. Then replaced the dead CMOS chips on the original PCB.
 
Ok I see. I'll keep that in mind about designing for the capacitor arcing between terminals. In this case, I think power density would be best by ensuring I have enough creepage/clearance.

If I place the terminals end to end, the terminals will be at the same potential. However, Cree claims that rotating them 180 degrees so the terminals are near each other gives the lowest inductance. I'm interested in understanding the implications of this on the capacitor insulation. We know the voltage of the terminals but we do not necessarily know the voltage of the floating case. If we assume the case is at the worst case, that puts the cases at 0 V and 4 kV in this example. The terminals are further in from the case so it may be possible to meet IPC-2221guidelines while still placing the capacitors right next to each other. So I'm wondering if designers typically consider the possible high voltage between the cases, or is it generally ignored. I haven't seen anyone discussing it so I'm leaning toward it is not considered.

I've attached the cap model that I'm looking at.
 

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First the disclaimers:
There are basically 3 general design considerations at play -

1) Safety. Whether or not you are required to get agency approvals, you need to follow design guidelines to protect people. For high voltage this really doesn't have much to do with your HV circuit, it's about separation. You should assume that bit of the HV circuit is dangerous and keep it away from accessible circuits.

2) Performance. Does your circuit work well when it isn't broken.

3) Reliability. Will it work properly for a long time (or enough time, really).

So, with regard to reliability - The capacitors you buy need to be able to withstand the HV stress they are rated for. Your concerns about insulation are well founded, but I think the worst case for internal insulation is the potential between the leads. I would use that spacing as you guideline. The component manufacturer would go out of business (so to speak) if they had breakdown in/over any part of their part when installed and maintained as intended. However, I would also avoid unnecessary external voltage stress to the part. Some manufacturers (not many) will specify the dielectric strength of the enclosure, you can look for that. You could also do some creative testing with a hi-pot or similar to see if you think the part is rugged in your configuration. It is also worth destroying one by taking it apart just to see how it's built.

I'm not 100% sure I understood your concerns about capacitor insulation, though. Ask a more specific question, if you like.

Finally, I'm sure you know this (and others have referred to it) but if not, review the difference between creepage and clearance for spacing requirements. The creepage numbers can get surprisingly big.
 
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Thanks for the disclaimers. I consider all parts of my circuit to be energized at the component or power supply voltage. Everything is discharged and HV is grounded before the circuit is handled. In my case, the circuit will still work if this piece of it is broken. Other capacitors will be overvoltaged <10% but I would expect a reduction in lifetime based on mean time between failure (MTBF) calculations available for film capacitors. That leads into point 3...they will still be reliable enough as I do not expect them to work for 100,000+ hours. Those are all good things to keep in mind though. Also, creepage and clearance was taken into consideration using UL 60950-1-07. Since the material group is unknow/unreliable, materials IIIa, IIIb and pollution degree 3 was assumed.

The component lead spacing is really large. For instance, one specific 1.5 kV capacitor (disregard the 2 kV discussion above) that I've considered has a lead spacing of 37.5 mm whereas IPC-2221 only specifies 7.5 mm. I've attached a better diagram of what I am considering. Dimensions, spacing, and voltages are labeled. In this layout, I think the cases should be considered to give the highest differential voltage for the system since they are floating and we do not know what they are.

I think I'll tear one apart and see what it looks like inside. I doubt that insulation will fail by placing them in close proximity for my application, but I haven't found this consideration discussed anywhere and depending on the design I think it might actually be damaging. I think it's an important consideration when deciding capacitor layout for optimal power density as their proximity could effect total board capacitance for a given area and mutual coupling. I wanted to see if not considering the case spacing would be a huge oversight on my part but it doesn't seem like it is at this point...for this layout anyway. Thanks for all of the input.
 

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