PN junction - advanced modeling

[Enialis]

Hello, let's start with a standard question:

1) A silicon diode has been characterized and as result we have a built-in potential of 0.53 V and a zero-bias capacitance of 1.3 mF/m^2. Assuming an abrupt junction (the measured grading coefficient is 0.5!) what are the respective doping levels on the p and n side? I don't find any real value that satisfies this condition...so how is it possible in a real device to have this values?

Now the non-standard:

2) In a p-n junction with linearly graded profiles anyone knows about the space charge region at equilibrium. What happen during a biasing? What about the electric fields inside the semiconductor?

3) How to use the result of a PN junction for the real 3D structure? I mean...what is considered as "Area" and what as "p-side length" or "n-side length" assuming a parallelepiped diffusion?

Any discussion is really appreciated.
Thank you

 

[eljose79]

for starting this discussion on the characterization of a silicon diode and its behavior in a p-n junction. I am a scientist with expertise in semiconductor device physics and I would be happy to provide some insights on your questions.

1) For a silicon diode with an abrupt junction and a built-in potential of 0.53 V, the respective doping levels on the p and n side can be calculated using the following equations:

NA = ND * exp(qVbi / (kT) * (1 - 1/2*mg))

where NA and ND are the acceptor and donor doping concentrations, q is the elementary charge, Vbi is the built-in potential, k is the Boltzmann constant, T is the temperature, and mg is the grading coefficient. The equation for the zero-bias capacitance can also be used to verify the doping levels. The values obtained may not match exactly due to experimental error and variations in the fabrication process.

2) In a p-n junction with linearly graded profiles, the space charge region at equilibrium is wider compared to an abrupt junction due to the gradual change in doping concentration. When the junction is biased, the space charge region narrows on the side with majority carriers and widens on the side with minority carriers. This results in a depletion region, where there is a lack of free carriers, and an electric field is established to maintain charge balance. The electric fields inside the semiconductor also change due to the applied bias, causing a change in the potential energy barrier at the junction.

3) The result of a p-n junction can be used to analyze the behavior of a real 3D structure, such as a parallelepiped diffusion. The "area" in this case would refer to the cross-sectional area of the junction, while the "p-side length" and "n-side length" would refer to the lengths of the p and n regions, respectively. These parameters can be used to calculate the current-voltage characteristics of the 3D structure and understand its behavior.

I hope this helps answer your questions and sparks further discussion on the topic. It's always exciting to delve into the intricacies of semiconductor devices and their behavior in different structures. Thank you for starting this conversation.