Relating Maxwell's equations to parasitic inductance due to layout

[dlang99099]

TL;DR Summary

How can I relate Maxwell's equations to parasitic inductance due to coupling between capacitors

I am trying to show how parasitic inductance is increased or decreased based on coupling between adjacent parallel capacitors. These capacitors are DC link capacitors so I'm not sure if that means it is not time varying and maxwells equations is no longer relevant?

 

[berkeman]

Summary:: How can I relate Maxwell's equations to parasitic inductance due to coupling between capacitors

I am trying to show how parasitic inductance is increased or decreased based on coupling between adjacent parallel capacitors. These capacitors are DC link capacitors so I'm not sure if that means it is not time varying and Maxwells equations is no longer relevant?

Welcome to PF.

Can you provide a bit more context? And if you can post PDF copies of the layout of the PCBA (along with the scale), that would be a help. Finally, what are the current levels and frequencies of the cross-coupling that you are wanting to calculate?

 

[dlang99099]

Welcome to PF.

Can you provide a bit more context? And if you can post PDF copies of the layout of the PCBA (along with the scale), that would be a help. Finally, what are the current levels and frequencies of the cross-coupling that you are wanting to calculate?

Thanks Berkeman.

I will be laying out my circuit later so I do not have a PDF yet. I would like to solve this analytically so I can see the general change different layouts will produce. I could simply create multiple layouts and use FEA like Maxwell Q3D to find best layout but I would like to use maxwells equations to get a little more insight into what's actually happening in that sense.

 

[Baluncore]

How can I relate Maxwell's equations to parasitic inductance due to coupling between capacitors
These capacitors are DC link capacitors

Maxwell's equations are separated too far from circuit physical layout to be useful.

You must design the layout sensibly, and calculate or estimate the inductive coupling. You might use a FEM simulation, but it should not be necessary.

Experience in layout is valuable. If you give us more details we can probably help refine your layout. There is no such thing as perfection.

 

[dlang99099]

I wouldn't be considering the path through the traces. I'm wanted to show how capacitor orientation and their orientation effect the loop inductance. I know how to look at it and tell which one is the better layout in general but I'd like to be able to quantify by how much.

Parallel capacitors rotated 180 degrees to the other should have the lowest coupling between the two since current would be in different directions, right? The problem with that is if you're using something like SMD capacitors that can be really close together, you may need to separate them enough to make sure you meet clearance/creepage requirements since the + and - terminals are right next to each other. Increasing the spacing will decrease your available area by some factor.

Would you be better off not rotating them 180 degrees and saving space for a few extra capacitors? There are a number of scenarios that can be considered so I would like to look at this from the coupling approach.

 

[Baluncore]

Parallel capacitors rotated 180 degrees to the other should have the lowest coupling between the two since current would be in different directions, right?

You will find that inductive coupling of capacitors is not a problem when you consider the inductance of the traces necessary to decouple their inductance. The capacitor inductance is swamped by the capacitance, so it is usually ignored. A PCB mount capacitor has leads that cancel the inductive magnetic field since the currents are equal and opposite.

Consider a square of ground plane, with a square of power plane on the layer above. You can mount parallel caps on that square with arbitrary component orientation. Simple parallel would make the parallel cap leads look like the edges of a wide, low-inductance strap.

Now consider electrical anti-parallel, reversed orientation, then the parallel components look like a common mode transformer with sum zero flux.

90° orientation would give asymmetric coupling of the parallel capacitors.

 

[dlang99099]

There is a paper titled "A Study of Integration of Parasitic Cancellation Techniques for EMI Filter Design With Discrete Components" that investigated something very similar to what I'm trying to do except there were no analytical equations to show the coupling. I am trying to do something similar but analytically using maxwells equations. I think it would be faradays law specifically but I'm not sure how to apply this in my situation.

 

[dlang99099]

You will find that inductive coupling of capacitors is not a problem when you consider the inductance of the traces necessary to decouple their inductance. The capacitor inductance is swamped by the capacitance, so it is usually ignored. A PCB mount capacitor has leads that cancel the inductive magnetic field since the currents are equal and opposite.

Consider a square of ground plane, with a square of power plane on the layer above. You can mount parallel caps on that square with arbitrary component orientation. Simple parallel would make the parallel cap leads look like the edges of a wide, low-inductance strap.

Now consider electrical anti-parallel, reversed orientation, then the parallel components look like a common mode transformer with sum zero flux.

90° orientation would give asymmetric coupling of the parallel capacitors.

Based on a few papers I've found on IEEE, that is not quite the case. There will still be coupling between nearby components. The paper I listed above was citing another paper where they said rotating the capacitors 90 degrees reduced the inductance from 89.3 nH to 7.5 nH giving a 90% reduction. Although traces play a large part in it, their coupling is still something that I would like to consider. If there is no large effect, I sould be able to find that out after solving.

 

[Baluncore]

There is a big difference between EMI filters and DC link capacitors. The inductor appears to be the major coupler. A lump of ferrite close to two capacitors is expected to increase inductive coupling of the capacitors. But that inductor is not present in the DC link.

Where there is a deep null, it is possible to fine tune the simulation to get total cancellation, and so claim huge improvements. But that is an unrealistic ideal that might be approached, but can never be achieved in a real manufactured product.

It is easy to claim Maxwell's equations are important since all EM is based there, but you shouldn't have to go that far back. The equations for mutual inductance between thin wires will do for the modelling of parallel capacitors. The GMD of the wire elements keeps Maxwell's equations at bay.

For the mutual coupling equations between thin wires I find the old references are the best.
For the mutual inductance between wires, based on the GMD of the wires:
“A Treatise on Electricity And Magnetism” By James Clerk Maxwell. See: article 692, (Vol 2).
Also:
“The Theory And Practice Of Absolute Measurements In Electricity And Magnetism” By Andrew Gray, M.A. 1893. See Chapter IV. General Theory Of Current Induction And Electromagnetic Action.
https://en.wikipedia.org/wiki/Inductance#Mutual_inductance

 

[Baluncore]

There is a wealth of formulas in the BBS from 1900 to 1920, now NIST documents.
For example;
BBS Vol 4, No 2. The Self and Mutual Inductances of Linear Conductors. Rosa[1907]
BBS Vol 8, No 1. Formulas for Self and Mutual Inductance,

Formulas And Tables For The Calculation Of Mutual And Self-Inductance [Revised]
By E. B. Rosa, and F. W. Grover. [1916]
Scientific Papers of The Bureau of Standards. No. 169.
https://archive.org/details/formul812871912169169unse

The field was summarised in the Book by Grover;
“Inductance Calculations. Working formulas and tables”. By; F. W. Grover.
Publisher: Instrument Society of America, Year: 1973. ISBN: 0-87664-557-0
See chapters 6, 7 & 8 for mutual inductance between thin wire elements.

 

[DaveE]

I wouldn't be considering the path through the traces.

But you will have to.

Since you are concerned with magnetic coupling, I'll phrase my answer in terms of transformers. While we haven't really seen your layout (which is really the whole point, isn't it?), I am pretty confident in saying that the magnetic coupling is relatively poor. Magnetic effects will be dominated by the uncoupled inductance "leakage inductance". This is primarily determined by how far the electrons have to travel, whether they are traveling along a Cu trace or across a capacitor is mostly irrelevant. Consider, for example, that capacitors tend to have a very short path through the dielectric, they are mostly built out of "traces", i.e. conductors, too. Reorienting capacitors is almost entirely equivalent to rerouting traces.

Perhaps you have a particularly unique problem. In which case I'd like to hear more about why it's different that all of the other PCB layouts we've all done. Otherwise, I think you are mostly wasting your time with this. Real engineering is the "art of approximation", doing good enough fast enough. In practice, I would just focus on minimizing trace length over the critical paths.

BTW, I have done work in designs where you orient multiple inductors in an orthogonal fashion to minimize coupling (for optimal filter design). That really does matter, for obvious reasons.