Engineering The connections in designing an I/O interface with output port

[Fatima Hasan]

Homework Statement

You want to design an I/O interface with one input port using the standard LS373 used in all class examples. The connections to the LS373 are as follows
The “D” pins are connected to the Device, the “Q” pins to the data bus, the “E” control to the device, and " top enclose O E end enclose " to the address decoder

What if an output port is used instead of input port?

Relevant Equations

-

The connections are as follows:
The "D" pins are connected to the data bus, the "Q" pins to the device, the "E" control to the block address decoder, the "OE(bar)" to ground.
Am I right?

 

[berkeman]

Homework Statement:: You want to design an I/O interface with one input port using the standard LS373 used in all class examples. The connections to the LS373 are as follows
The “D” pins are connected to the Device, the “Q” pins to the data bus, the “E” control to the device, and " top enclose O E end enclose " to the address decoder

What if an output port is used instead of input port?
Relevant Equations:: -

The connections are as follows:
The "D" pins are connected to the data bus, the "Q" pins to the device, the "E" control to the block address decoder, the "OE(bar)" to ground.
Am I right?

Can you post a diagram or drawing of all of this? It's a bit hard to follow unless I make some guesses. You can use the "Attach files" link below the Edit window to upload a PDF or JPEG copy. Thanks.

 

[Fatima Hasan]

Can you post a diagram or drawing of all of this? It's a bit hard to follow unless I make some guesses. You can use the "Attach files" link below the Edit window to upload a PDF or JPEG copy. Thanks.

Thanks for your reply.

 

[Frodo]

I am not sure I even understand what you are being asked to do.

A 74LS373 device is a latching device. See its data sheet.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The outputs Q0 - Q7 follow the inputs D0 - D8 until the device is clocked when the outputs are locked at the last value. Hence, as the input varies, the output will remain at the clocked value.

The outputs are passed to the 74LS373 where they are presumably clocked and latched in the device. The 74LS373 then drives the LED display.

Hence the LED display will not flicker - it will show the last clocked value.

I suspect the whole of the circuit in red is the clocking signal used to sample the input data. You don't give a part number for U1 so it is difficult to know what it does but I suspect it is a 16-bit counter counting upwards and the 8-input NAND gate flips when the given count on bits A3-A9 (ie 1001010) is reached and sends the sampling signal. The 3 least significant bits A0-A2 change the fastest and pass to U3.

Note something very important about the NAND.

Its output goes to LO when ALL inputs are HI. When A3 goes from HI to LO it causes A4 to go, say, from LO to HI after a short delay. This tiny delay on every count ensures that the NAND will never give a transient false LO and will reliably give an output when the desired count is reached. (You will need to think if the inverters invalidate this - it is correct without them).

It looks like the sampling circuit uses the varying output from U6 to clock the counter U1 as otherwise I don't see why the output of U6 should be fed to it. Also, it seems there is no clock signal generator unless U1 has one in it. However all will be revealed when you give the part number for U1.

The 74LS138 is a very high speed decoder.

This 74LS138 IC has 3-binary select inputs like A, B, & C. If the IC is activated, then these input pins will decide which of the 8 usually HIGH o/ps will go LOW. The enable pins are two active low & one active high.

 

[Tom.G]

What is the function of the "E" pin on U6?
Doesn't it need to be connected somewhere?

The rest of it looks OK to me.

Cheers,
Tom

p.s. for those not familiar with microprocessor circuits/signals:
1) U1 is a microprocessor with D0-D7 being the bi-directional databus I/O;
2) A0-A15 the address bus outputs;
3) -IOR, -IOW are negative-logic signals indicating that the address bus holds I/O port numbers (R for Read, W for Write), rather than memory addresses.
4) U3 and the gates between it and U1 are an address decoder. The U3 outputs are used to select which I/O device to enable depending on the address bus contents from the CPU, U1.

Cheers,
Tom