Timing Diagrams for D Flip-Flops

[STEMucator]

Homework Statement

Complete the timing diagram for the following circuit:

Homework Equations

The Attempt at a Solution

So I was doing some pre-midterm studying, and I was slightly confused with the operation of this circuit.

I think part of the solution provided is incorrect, but I'm not positive so I thought I would ask. Here is my attempt so far at filling in the waveforms:

I believe the value of $B$ provided at that clock edge is incorrect (the place where I have not connected the lines).

At that rising clock edge, the rising edge triggered D flip-flops will start by copying the value of $\bar x$ into $A$. Hence why $A = 1$ at that clock edge.

Then looking at the NOR gate before the second D flip-flop, the inputs should be $A = 1$ and $x = 0$. This results in $0$. Should this not imply that $B = 0$ and not $B = 1$ as they have provided?

EDIT: I also forgot to ask, does synchronous reset have any impact on a rising edge triggered D flip-flop for a falling clock edge? I have ignored the reset in the early portions of the waveform because it was a falling clock edge.

 

[STEMucator]

Wait wait, I think I see how I was reading the diagram incorrectly before. Would this be the answer:

 

[milesyoung]

These are positive edge-triggered?

To me it looks like B should be low at all times, since either x or A is high on CLK. C should then be high after first CLK until reset, since x AND B is never true.

 

[STEMucator]

These are positive edge-triggered?

To me it looks like B should be low at all times, since either x or A is high on CLK. C should then be high after first CLK until reset, since x AND B is never true.

Yes, these are rising edge triggered (probably master-slave d-latch) D flip-flops. So when the CLK is high, the master is transparent and the slave is latched.

I also thought $B$ should be low at all times at first, but they provide part of the solution, and $B$ goes high at one point. This changed the way I interpreted the diagram.

If $B$ really does go high at the point they have indicated, then the only way that could happen is if they are sampling the values of the input variables $x$ and $A$ just before the rising clock edge.

So for the point where $B$ goes high in the solution they provided, I read it like so:

$x = 0$ before the rising edge.
$A = 0$ before the rising edge.

$0$ NOR $0$ is $1$, therefore $B = 1$ just after the rising edge.

I think this is because of the operation of the actual D flip-flop itself. They way it sends the values through just after the clock goes high, but it samples them a very small instant just before the clock goes high.

Therefore, I believe the image in post #2 is correct.

 

[CWatters]

I agree with the wave form for B in post #2.

The data on D is sampled on the rising edge of the clock only. The data must be valid for a short time (Tsetup) before the rising edge and held for a short time after the rising edge (Thold). Apart from that changes to D at any other time do not effect Q.

So looking at the second latch...

Just prior to the first rising edge of clk... X = 0 and A = 0. So the data input to the latch will be 1. That means after the rising edge B = 1.
Just prior to the next rising edge of clk .. X = 0 but A = 1. So the data input to the latch will be 0. That means after the rising edge B = 0.
etc

 

[CWatters]

PS Normally the output of a latch will take time to change after the clock edge. This delay plus the NOR gate delay helps ensure that Thold is met for the next latch in the chain.

 

[milesyoung]

I think this is because of the operation of the actual D flip-flop itself. They way it sends the values through just after the clock goes high, but it samples them a very small instant just before the clock goes high.

Therefore, I believe the image in post #2 is correct.

I took the view that the flip-flops were transparent on positive-edge CLK, but that doesn't make any sense, since they then wouldn't function as delay elements. Apologies.

 

[CWatters]

An example would be the 7474.