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Dividing the CLK frequency by 8

  1. Feb 26, 2015 #1

    Zondrina

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    1. The problem statement, all variables and given/known data

    The question and provided answer are given:

    Screen Shot 2015-02-26 at 11.12.00 AM.png

    2. Relevant equations


    3. The attempt at a solution

    I disagree with the answer. Shouldn't there only be three rising edge triggered d flip-flops?

    I say this because I know if I only had one d flip-flop with the inverter, the clock frequency would be cut in half.

    Similarly, I would assume that having two d-flip flops with the inverter would cut the clock frequency by 1/4.

    So would I not need three d flip-flops to cut the frequency by 1/8?
     
  2. jcsd
  3. Feb 26, 2015 #2

    Svein

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    You can do it several ways, but if the clock input is common to all FFs, you need a more complicated gating than mere inverters can supply.
    04353.png
    This is an example of a synchronous counter.
    ee17.GIF
    If the clock inputs are freely available, you can make an asynchronous counter like this.

    BTW, the solution you have been presented with is usually called a ring counter. It is simple to create, but it has several illegal states which must be dealt with - and they have not been dealt with.
     
  4. Feb 27, 2015 #3

    Zondrina

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    You know. After just sitting around for a while, I just made a pretty important connection between FSM design and this problem.

    I realize a state graph would be appropriate, from which a state table and corresponding circuit could be derived. Since the output relies on the clock, Moore outputs would be appropriate. Here's another way of producing the circuit, it uses more gates, but it works:

    IMG_0547.JPG

    Produced with saving the environment in mind.
     
  5. Feb 28, 2015 #4

    Svein

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    You are on your way to discovering the Grey coding. In a binary counter, several bits may change at the same time (011→100), but in the Grey code sequence, only one bit changes in each step. A three-bit Grey counter may go like this: 000→001→011→010→110→111→101→100(→000).
     
  6. Feb 28, 2015 #5

    Merlin3189

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    "I disagree with the answer. Shouldn't there only be three rising edge triggered d flip-flops?"

    Yes.

    What does one D flip-flop do?
    How do you connect "three rising edge triggered d flip-flops" so that they do what you want.

    Please forget about synchronous counters, ring counters, binary codes, etc. All you want to do is divide by 8.
     
  7. Feb 28, 2015 #6

    CWatters

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    The answer circuit is correct assuming that the Q output of each latch is connected to the D input of the next (and you add a reset input to all the latches).

    The Q outputs follow this pattern...

    0000
    1000
    1100
    1110
    1111
    0111
    0011
    0001
    0000
    etc
    So the any of the Q outputs are equivalent to clk/8.

    If there was only three latches the pattern would be

    000
    100
    110
    111
    011
    001
    000
    etc

    You could build one using three latches but I think it would be somewhat different to the answer circuit.
     
  8. Mar 1, 2015 #7

    Merlin3189

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    I'm a bit puzzled. The "answer" looks like a sort of shift register, which certainly wouldn't divide by 8. I said OP was correct in saying that answer was wrong. OP's argument that one flip flpo divides by 2 , so 3 flip flops divide by 8 is exactly correct.

    I still don't see what all those tables of binary codes have to do with dividing by 8. What OP needs is to take a serial pulse stream and produce a symmetric output pulse stream with 1/8 the number of pulses - no codes, no binary.
    And they can do that simply with 3 D flip flops, no inverters, no gates, no feedback, no maths beyond what they've already said - 23 = 8.

    If OP is still interested, maybe they could show how they divide by 2 using one D flip flop, and LABEL the input clock signal and the output clock signal.
     
  9. Mar 2, 2015 #8

    Svein

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    Well, no. The "answer" is a ring counter, a simple synchronous circuit. The ring counter is characterized by:
    • Only one bit changes at each clock pulse, which means no glitches on the outputs
    • If you have n FFs, the circuit divides by 2n, not by 2n
    • If n > 2, a full circuit incorporates a watchdog circuit to eliminate illegal internal states
    See post #2.
     
  10. Mar 2, 2015 #9

    CWatters

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    Yes it does.

    The answer circuit is not wrong it's just different to your proposal.

    Presumably you are proposing an asynchronous (aka ripple) counter? That works but has some limitations. Are you proposing to make a synchronous counter? I think you need additional gates and for this question you are only allowed inverters for free.

    The answer circuit is synchronous and only uses an inverter.

    Look again. Perhaps it helps if I add headings Q1 to Q4..

    Q
    1234
    0000
    1000
    1100
    1110
    1111
    0111
    0011
    0001

    You have four outputs Q1 to Q4 all of which are 1/8th of the clock. (eg they are low for four clk cycles and high for four clock cycles). The outputs are also synchronous with the input clk. The problem statement didn't limit you to three latches.
     
  11. Mar 2, 2015 #10

    Merlin3189

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    It's not really a question for me, rather for the OP, but I still don't understand why you are all getting so complicated.
    The original "problem statement, all variables and given/known data" simply asked to produce an output which had 1/8 the frequency of the input clock - a very common circuit requirement. There was no requirement for synchronous output, but an apparent desire for simplicity and a specific requirement to minimise extra gates.
    While I do not know that a bog standard 3-stage ripple counter is the desired answer (if indeed there is a specific required answer), it is a pretty good guess.
    As for the suggested answer (in the words of Wikipaedia, a "type of circular shift register." known as a ring counter), I simply agreed with the OP that this answer was wrong - it does not meet the problem specification, because, (1) it has no output, (2) it does not divide by 8 and there is no point in that circuit where a clk/8 signal COULD be taken from, and (3) it is not a minimal solution having an extra gate and an extra FF.
    I still cannot understand the CWatters comment, "The answer circuit is correct assuming that the Q output of each latch is connected to the D input of the next (and you add a reset input to all the latches)." As there are 4 FFs, even connecting them correctly either divides by 16 or wastes gates. And saying that an answer is "correct" IF you change the connections and add extra circuitry, seems to be stretching the meaning of "correct" rather a long way!

    I did not deny that any of your complex circuits would do something and in fact I did no more than glance at them to see that they were irrelevant to the problem.

    I hope I did not propose a circuit (as CWatters suggested in his, "The answer circuit is not wrong it's just different to your proposal.") OP was almost there in giving a full and complete answer to the original question and just needed encouragement to pursue their own ideas to the logical conclusion. I was dismayed by all the irrelevant erudition in other posts, which could only serve to obscure the issue and distract OP from a good simple solution along the lines they were already thinking. And to use 4 bit counters seemed like deliberate misinformation.

    Since OP is no longer participating, I think I shall leave you to it, as there is nothing to be gained by our arguing about anything.
     
  12. Mar 2, 2015 #11

    Svein

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    I suggest you check out the data sheet for CD4022.
     
  13. Mar 3, 2015 #12

    Merlin3189

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    Yes, a lovely circuit, as are all the 7400 and CD4000 range. I bet many youngsters these days would automatically reach for a microcontroller to do the jobs that some of these chips did.

    But I'm getting off the point. I think we must be a bit at cross purposes. Whatever this chip does, it takes 4 FFs and I think I count 14 extra gates, so for me it is hardly a good answer to the question, which can be answered with 3 FFs and 0 extra gates.

    I had assumed the OP was doing some sort of electronics course and learning about logic - in the abstract sense. Perhaps you have taken the question as a more practical one like, what chip should I use to do this job with minimum package count. In that case, you may well be right and I could only complain that, 1- there is no indication of where the output can be taken, and 2- the circuit as originally sketched is very incomplete, so it is still not a good answer.

    And as I said, OP is long gone, you obviously know at least as much as me (& probably much more) about this topic, so there is no point in our arguing about what they might have wanted. We both came here to help and now the need has disappeared, let's move on.
     
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