Understanding Full Adders in Verilog: Code Explanation and Help Request

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The discussion focuses on understanding the code for a 4-bit full adder in Verilog, particularly the line "fulladder f1(SW[5],SW[1],a,LEDG[1],b)." The user expresses confusion about the implementation and functionality of carry adders, noting that their textbook lacks clarity. They seek assistance in comprehending this specific line of code, which is frequently encountered but poorly explained in resources. A suggested link was provided to help clarify the topic further. Overall, the conversation highlights the need for better educational resources on Verilog full adders.
polaris90
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We are currently working with full adders in my logic circuits class.

I have the following code for a 4-bi full adder, however I'm having trouble understanding it and my textbook does a poor job at explaining the carry adders. fulladder f1(SW[5],SW[1],a,LEDG[1],b);this is the only line that I don't understand. I've seen this kind of code several times but no-one explains it. Can someone give a hand?
 
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polaris90 said:
fulladder f1(SW[5],SW[1],a,LEDG[1],b);


this is the only line that I don't understand. I've seen this kind of code several times but no-one explains it. Can someone give a hand?
A google search turned up this: http://www.expertcore.org/viewtopic.php?t=767[/color]

I think that should help a bit. :wink:
 
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