Creating a ParityBuild Circuit Module

In summary, a ParityBuild Circuit Module is a type of circuit module used to check for errors in data transmission by ensuring the number of 1s in a data block is always even. It works by counting the number of 1s and adding a parity bit to the end, and can detect and correct errors when the data is received. The main advantage of using this module is its ability to ensure accuracy and reliability in digital systems, while being relatively simple and cost-effective. However, it has limitations in detecting and correcting only one-bit or odd number of bit errors. ParityBuild Circuit Modules can be implemented using logic gates or incorporated into digital systems as a built-in feature, but careful design and testing is necessary for their effectiveness.
  • #1
tomizzo
114
2

Homework Statement



Create a circuit (a module) called ParityBuild. It takes a parameterized input that is n bits wide. The ParityBuild module then examines the input bit stream and determines the parity (use even parity). The output is a bit stream that is n+1 bits wide, with the parity bit appended as the MSB to the input stream. (Do not use any parity functions… write your own code to count the number of 1s. Is there an easy way to do this?). Simulate your design with at least three different input values to verify correct operation.

Homework Equations



None

The Attempt at a Solution



When I simulate the code, I get the output to replicate the entire input, but I can't seem to add the additional digit out front. When I simulate, the most significant bit is not assigned to anything. The following is the code that I did,

NOTE: I'm pretty sure the problem exists in line 18 and 27. The program is not assigning the bit values for what I want them to be.

1 module ParityBuild(inputStream,outputStream);
2 parameter n = 8;
3 integer k;
4 integer count = 0;
5 input [n-1:0] inputStream;
6 output reg [n:0] outputStream;
7
8 always @(inputStream)
9 begin
10 for(k = 0; k < n; k = k + 1)
11 begin
12 if(inputStream[k] == 1'b1)
13 count = count + 1;
14 end
15
16 if(count%2 == 0)
17 begin
18 outputStream[n]=1'b0;
19 for(k = 0; k < n; k = k + 1)
20 begin
21 outputStream[k]=inputStream[k];
22 end
23 end
24
25 else
26 begin
27 outputStream[n]=1'b1;
28 for(k = 0; k < n; k = k + 1)
29 begin
30 outputStream[k]=inputStream[k];
31 end
32 end
33 end
34
35 endmodule
 
Last edited:
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  • #2


To fix this issue, you can try the following code:

module ParityBuild(
input [n-1:0] inputStream,
output reg [n:0] outputStream
);

parameter n = 8;
integer k;
integer count = 0;

always @(*)
begin
count = 0; //reset count for every new input
for(k = 0; k < n; k = k + 1)
begin
if(inputStream[k] == 1'b1)
count = count + 1;
end

if(count%2 == 0)
begin
outputStream[n]=1'b0;
for(k = 0; k < n; k = k + 1)
begin
outputStream[k]=inputStream[k];
end
end

else
begin
outputStream[n]=1'b1;
for(k = 0; k < n; k = k + 1)
begin
outputStream[k]=inputStream[k];
end
end
end

endmodule

The changes made include:
1. Adding the input and output ports in the module declaration.
2. Changing the sensitivity list of the always block to (*), which means that the block will execute whenever any of the inputs change.
3. Resetting the count variable to 0 at the beginning of the always block, so that it is not affected by previous input values.
4. Adding the keyword "reg" before the output declaration, as it is being assigned a value inside the always block.
5. Removing the unnecessary begin-end blocks after the if statements.
6. Changing the if statement in line 16 to always execute, since the output should be assigned for every input.
7. Removing the extra endmodule statement at the end.
 

FAQ: Creating a ParityBuild Circuit Module

1. What is a ParityBuild Circuit Module?

A ParityBuild Circuit Module is a type of circuit module used in digital systems to check for errors in data transmission. It ensures that the number of 1s in a data block is always even, detecting and correcting any odd number of 1s.

2. How does a ParityBuild Circuit Module work?

A ParityBuild Circuit Module works by counting the number of 1s in a data block and adding a parity bit to the end to make the total number of 1s even. When the data is received, the module counts the number of 1s again and compares it to the parity bit. If they do not match, an error is detected and corrected.

3. What are the advantages of using a ParityBuild Circuit Module?

The main advantage of using a ParityBuild Circuit Module is its ability to detect and correct errors in data transmission. This ensures the accuracy and reliability of digital systems. Additionally, ParityBuild Circuit Modules are relatively simple and inexpensive to implement.

4. Are there any limitations to using a ParityBuild Circuit Module?

One limitation of ParityBuild Circuit Modules is that they can only detect and correct errors in data blocks with an odd number of bit errors. If there are an even number of bit errors, the module will not detect the error. Additionally, ParityBuild Circuit Modules can only detect and correct one-bit errors, so they may not be suitable for systems that require a higher level of error detection and correction.

5. How can I implement a ParityBuild Circuit Module?

ParityBuild Circuit Modules can be implemented using logic gates and other electronic components. They can also be incorporated into microprocessors and other digital systems as a built-in feature. It is important to carefully design and test the module to ensure its accuracy and reliability in detecting and correcting errors.

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