# Verilog Program

1. Oct 17, 2012

### tomizzo

1. The problem statement, all variables and given/known data

Create a circuit (a module) called ParityBuild. It takes a parameterized input that is n bits wide. The ParityBuild module then examines the input bit stream and determines the parity (use even parity). The output is a bit stream that is n+1 bits wide, with the parity bit appended as the MSB to the input stream. (Do not use any parity functions… write your own code to count the number of 1s. Is there an easy way to do this?). Simulate your design with at least three different input values to verify correct operation.

2. Relevant equations

None

3. The attempt at a solution

When I simulate the code, I get the output to replicate the entire input, but I cant seem to add the additional digit out front. When I simulate, the most significant bit is not assigned to anything. The following is the code that I did,

NOTE: I'm pretty sure the problem exists in line 18 and 27. The program is not assigning the bit values for what I want them to be.

1 module ParityBuild(inputStream,outputStream);
2 parameter n = 8;
3 integer k;
4 integer count = 0;
5 input [n-1:0] inputStream;
6 output reg [n:0] outputStream;
7
8 always @(inputStream)
9 begin
10 for(k = 0; k < n; k = k + 1)
11 begin
12 if(inputStream[k] == 1'b1)
13 count = count + 1;
14 end
15
16 if(count%2 == 0)
17 begin
18 outputStream[n]=1'b0;
19 for(k = 0; k < n; k = k + 1)
20 begin
21 outputStream[k]=inputStream[k];
22 end
23 end
24
25 else
26 begin
27 outputStream[n]=1'b1;
28 for(k = 0; k < n; k = k + 1)
29 begin
30 outputStream[k]=inputStream[k];
31 end
32 end
33 end
34
35 endmodule

Last edited: Oct 17, 2012