Hey Jim,
In an ordinary programming language the programmer often has the luxury of assuming that there is limitless memory available. When the program is run and it decides it needs a certain amount of memory, say for a string variable, it makes the request to the operating system. The operating system keeps track of how much memory is available, and who is using what, and will allocate a block to this program. Later, the program can notify the operating system that it no longer needs this memory, and it gets returned to "the heap".
Synthesizable Verilog kind of looks like a programming language but is actually a "hardware description language". It is really just a text way of doing what we did years ago with pencil, stencil, and D-size schematic sheet to design digital logic. If I needed a register big enough to hold a 32-bit word, I drew in 32 flip-flops on my schematic, then build my board. Today in verilog we "instantiate a 32 bit register" and program the FPGA. In both cases a piece of hardware has been created. And, just like there was limited real estate on my digital logic board, there are limited logic resources available within an FPGA, so we try to be very conservative (the point of the OPs post). If I change my mind and decide I needed it to be a 64-bit register, I have to change the verilog code, and reprogram the FPGA and hope that it can "fit" the design. If it needs to be 32-bit most of the time, and 64-bit occasionally, I need to build it with 64-bits.
Of course, this is somewhat simplified for clarity's sake. It is actually pretty unlikely that bumping a single register up in size by 32 bits would cause a fitting issue. Even modest FPGAs today provide tens of thousands of flip-flops.