What is Clock Pulse in Digital Circuits?

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Discussion Overview

The discussion revolves around the concept of clock pulses in digital circuits, particularly in relation to flip-flops. Participants explore the nature of clock pulses, their role in enabling state transitions, and the behavior of various flip-flop types, including SR and JK flip-flops. The conversation includes questions about definitions, operational mechanics, and the implications of specific input states.

Discussion Character

  • Exploratory
  • Technical explanation
  • Conceptual clarification
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • Some participants inquire about the meaning of clock pulses for flip-flops, questioning whether they serve merely as a supply voltage or have a more complex role in state transitions.
  • There is a discussion about the operation of chips that respond to clock signals transitioning from high to low, as opposed to low to high.
  • One participant seeks clarification on the term "next state" in the context of SR flip-flops, suggesting that it relates to state machines and the relationship between current and subsequent states.
  • Another participant points out the importance of avoiding undefined states in flip-flops, particularly when both set and reset inputs are high.
  • There is a mention of how JK flip-flops can toggle states based on previous outputs and the necessity of initializing the output before toggling.
  • Participants express confusion over specific statements regarding latch circuits and their behavior during clock transitions, particularly concerning invalid states and the timing of state changes.

Areas of Agreement / Disagreement

Participants express varying levels of understanding regarding the operation of clock pulses and flip-flops, with some points of confusion remaining unresolved. There is no clear consensus on certain technical aspects, particularly around the implications of undefined states and the initialization of feedback circuits.

Contextual Notes

Some participants highlight limitations in clarity due to spelling and grammar issues, which may affect comprehension of technical concepts. The discussion also reflects a dependence on specific definitions and contexts, particularly regarding state machines and flip-flop behavior.

Who May Find This Useful

This discussion may be useful for students and practitioners in electrical engineering and computer science, particularly those interested in digital circuit design and the functioning of flip-flops.

vvkannan
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wat is meant by the clock pulse given to the flip flops in digital circuits.
Is it just a supply that is given to the ic as long as it is held in on position.
How do some chips operate when the clock goes from high to low and not when pulses go from low to high?.
 
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vvkannan said:
wat is meant by the clock pulse given to the flip flops in digital circuits.
Is it just a supply that is given to the ic as long as it is held in on position.
How do some chips operate when the clock goes from high to low and not when pulses go from low to high?.


This article should help you understand flip-flops. If you have questions about the article, you can post follow-up questions here.

http://en.wikipedia.org/wiki/Flip-flop_(electronics )

.
 
Last edited by a moderator:
what is the 'nest stat'.how do we obtain it in 'SR flip flop'
 
The... what?

- Warren
 
vvkannan said:
what is the 'nest stat'.how do we obtain it in 'SR flip flop'

If you mean the NEXT STATE, this only makes sense within context of a (finite) state machine (be it a single flip flop, or not). The next state of a state machine is the one that follows from the existing state (or, if you're going backwards, the state prior to the current one). Symbolically, this is Q(t+1) (the state of the machine at time, or step, t+1) as it relates to Q(t) (the state of the machine at time, or step, t).

In context of the SR flip flop, this depends on the current state of machine, and the status of the S(et) and R(eset) inputs:
http://en.wikipedia.org/wiki/Flip_flop_(electronics)#Set-Reset_flip-flops_.28SR_flip-flops.29

Not to be a grammar/spelling nazi, but there are spelling mistakes, and then there are spelling mistakes that completely impair the comprehension (by others) of what you are trying to say.
 
MATLABdude said:
Not to be a grammar/spelling nazi, but there are spelling mistakes, and then there are spelling mistakes that completely impair the comprehension (by others) of what you are trying to say.

Pretty helpful EE spelling/grammar nazi in this case :biggrin:
 
Terribly sorry abt that.
Its 'next state'
 
The LATCH CIRCUITS use enabling inputs and these latch circuits are called flip flops when the enabling inputs r connected to pulse detectors thereby making the circuit to respond only at the transtion of enabling inuts called as clock pulses. IS THIS RIGHT?

THEY say that the invalid state for the S-R flip-flop is maintained only for the short period of time that the pulse detector circuit allows the latch to be enabled. After that brief time period has elapsed, the outputs will latch into either the set or the reset state.I CANT UNDERSTAND THIS STATEMENT.please hellp me
 
vvkannan said:
The LATCH CIRCUITS use enabling inputs and these latch circuits are called flip flops when the enabling inputs r connected to pulse detectors thereby making the circuit to respond only at the transtion of enabling inuts called as clock pulses. IS THIS RIGHT?

If you mean that states only transition of "enabling" inputs (i.e. clock), then yes.

vvkannan said:
THEY say that the invalid state for the S-R flip-flop is maintained only for the short period of time that the pulse detector circuit allows the latch to be enabled. After that brief time period has elapsed, the outputs will latch into either the set or the reset state.I CANT UNDERSTAND THIS STATEMENT.please hellp me

S=R=1 is an undefined condition, which must be avoided (at least, when there's a transition at the clock input). These "undefined states" must be avoided as it results in an unknown output (may be either 1 or 0, with no guarantee that it is one or the other). The J-K flip flop covers this case (J=K=1), and uses it to Toggle the state of the flip flop (if output is a 1, it gets set to 0, and vice versa).
 
  • #10
thx for ur reply dude.so if j and k r made 1 and clock pulse is given then the the output depends upon the feedback from the previous outputs.
if the previous state is set r reset then the present state is reset r set respectively and this continues r otherwise toggles.is this right?
if so wat if the circuit is used for the first time? (i think this applies to all the feedback circuits)
 
  • #11
vvkannan said:
thx for ur reply dude.so if j and k r made 1 and clock pulse is given then the the output depends upon the feedback from the previous outputs.
if the previous state is set r reset then the present state is reset r set respectively and this continues r otherwise toggles.is this right?
if so wat if the circuit is used for the first time? (i think this applies to all the feedback circuits)

Sorry, I have a hard time understanding if 'r' means aRe, or oR. If it is 'are', then when dealing with the singular (as opposed to the plural), this should also be 'is' (the input is set high vs. the inputs are set low).

Grammar lesson aside, yes, J=K=1 toggles the output. You need to initialize the value first (set the output Q to either 0 or 1), however, or you toggle whatever the output is initially set to (something random).
 

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