From Wikipedia:
http://en.wikipedia.org/wiki/Apollo_Guidance_Computer
AGC [Apollo Guidance Computer] in Apollo
Each flight to the Moon (with the exception of Apollo 8, which didn't take a Lunar Module on its lunar orbit mission) had two AGCs, one each in the Command Module and the Lunar Module. The AGC in the Command Module was at the center of that spacecraft 's guidance & navigation system (G&C). The AGC in the Lunar Module ran its Primary Guidance, Navigation and Control System, called by the acronym PGNCS (pronounced pings).
Each lunar mission had two additional computers:
The Launch Vehicle Digital Computer (LVDC) on the Saturn V booster instrumentation ring, and
the Abort Guidance System (AGS) of the Lunar Module, to be used in the event of failure of the LM PGNCS. The AGS could be used to take off from the Moon, and to rendezvous with the Command Module, but not to land.
Design
The AGC was designed at the MIT Instrumentation Laboratory under Charles Stark Draper, with hardware design led by Eldon C. Hall.[1] Early architectural work came from J.H. Laning Jr., Albert Hopkins, Ramon Alonso,[2] [3] and Hugh Blair-Smith.[4] The flight hardware was fabricated by Raytheon, whose Herb Thaler[5] was also on the architectural team.
The Apollo flight computer was the first to use integrated circuits (ICs). While the Block I version used 4,100 ICs, each containing a single 3-input NOR gate, the later Block II version (used in the crewed flights) used 2,800 ICs, each with two 3-input NOR gates.[1]:34 The ICs, from Fairchild Semiconductor, were implemented using resistor-transistor logic (RTL) in a flat-pack. They were connected via wire wrap, and the wiring was then embedded in cast epoxy plastic. The use of a single type of IC (the dual NOR3) throughout the AGC avoided problems that plagued another early IC computer design, the Minuteman II guidance computer, which used a mix of diode-transistor logic and diode logic gates.
The computer had 2048 words of erasable magnetic core memory and 36 kilowords of read-only core rope memory. Both had cycle times of 11.72 micro-seconds. The memory word length was 16 bits: 15 bits of data and 1 odd-parity bit. The CPU-internal 16-bit word format was 14 bits of data, 1 overflow bit, and 1 sign bit (ones' complement representation).
