Design BCD 2-out-5 Encoder Using Logic Gates - 74210 Code

[weeds]

Can anyone please help with the design of a BCD 2 out of 5 encoder (74210 code) using basic logic gates

 

[Ouabache]

You have a very interesting digital project.

It is not clear from your question, what you have in mind.
Can you elaborate a bit on your project? Of course we are not here to do your homework, but certainly willing to steer you in the right direction.

What have you done so far on this? (are you familiar with basic logic gates, do you know what BCD and encoders are?)

 

[weeds]

Thanks for the reply:
I am familiar with Logic gates.I think the confusion is the BCD.I understand that a decimal number (0 to 9) is being represented by 1's and 0's.I am not sure how many inputs and outputs I should have and the mapping on a K-Map.See attchement for the truth table I must complete.This is the source of my misery.

I am required to design a BCD to 2-out-of-five- encoder.

DEC A B C D P7 P4 P2 P1 P0
0
1
2
3
4
5
6
7
8
9
ALL OTHERS 0 0 0 0 0 0 0

The above is supposed to be a truth table for the encoder (without boxes!)

 

[Ouabache]

Ok, on the BCD, yes decimal numbers are from 0 - 9, so what is the minimum number of bits you would need to represent 10 characters?

hint: 2 bits: 00, 01, 10, 11 ( or 2^2) could represent 0, 1, 2, 3
3 bits: 000, 001, 010, 011, 100, 101, 110, 111 ( or 2^3) could represent 0, 1, ... 7

In your description you mention 74210 code. Is that a coding scheme for BCD numbers?

To give you some ideas for your truth table, take a look at one on this spec sheet
---> http://www.datasheetarchive.com/datasheet/pdf/59/59104.html
this one happens to be for an 8-to-3 encoder.

 

[weeds]

Thanks for the reply.My input is a 4 bit number i.e 0001,0010,0011 etc till count ten.The 74210 code goes something like this,11000,00011,00101,00110,01001,01010,01100,10001,10010 and 10100(these correspond to P7,P4,P2,P1,P0).It has got two 1's for parity checking or error detection.I have done the kMaps (any hints on kmaps) and drew the circuits.I am left with building the circuit using micro cap and testing.I would welcome ant hints.Thanks

 

[pervect]

If you've done the maps, you should have a Boolean logic expression that represents your truth table - or haven't you gotten that far?

 

[Ouabache]

Thanks for the reply.My input is a 4 bit number i.e 0001,0010,0011 etc till count ten.The 74210 code goes something like this,11000,00011,00101,00110,01001,01010,01100,10001,10010 and 10100(these correspond to P7,P4,P2,P1,P0).

Okay i follow you now.. The ABCD is a 4 bit binary-coded-decimal, and your P7,P4,P2,P1,P0 is the 5 bit (74210 code)

(74210 code) is also known as the POSTNET Barcode
see ---> http://www.kuro5hin.org/story/2002/4/12/21757/8647

You mention: ALL OTHERS 0 0 0 0 0 0 0
Do you mean: your design criteria specifies that input values 1010 thru 1111 all have output values of 0 0 0 0 0? Or do you have flexibility to choose them as "don't care" conditions (X)? (if so, that would certainly simplify your logic)

It has got two 1's for parity checking or error detection.

Are you also incorporating the parity check into your digital logic??

I see plecompte is designing the same encoder and looking for clues on another forum. Perhaps you are following that too.. ----> http://forum.allaboutcircuits.com/index.php?showtopic=1614

 

[Ouabache]

If you created Kmaps (without using don't care conditions for inputs 1010 thru 1111) what logic expressions did you get for P0, P1, P2, P4, & P7?

I also made Kmaps & obtained expressions for your 5 outputs (without using don't care conditions) and can give you feedback?

 

[weeds]

Ouabache!Thanks so much for the help.I have never researched anything the way I did about this particular assignment.Thanks for not telling me the answer.I managed to get the 5 output equations for P0 through to P7 using KMaps.Using micro cap I drew the circuit (logic) fed my inputs A,B,C and D and what I got as outputs (P7...) matched my Truth table.
I might have a few more gates than required but I am definitely onto it.I did not use don't cares .

And Pervect can you tell me more about "ab caNeffg DehNiD jN kal " it's a new one.

Thanks Guys

 

[Ouabache]

You're welcome.. I think we are all here to learn something and if we help some folks along the way, that's a bonus..

 

[ALJ]

Kmaps expressions

Ouabache,
What were the expressions that you produced from your Kmaps. I am also struggling with the same problem as weeds.

I have produced the truth table but am having a bit of difficulty with the Kmpas and logic diagrams for the BCD to 74210 encoder.

Any assistance would be appreciated.

ALJ

 

[Ouabache]

Ouabache,
What were the expressions that you produced from your Kmaps. I am also struggling with the same problem as weeds.

I have produced the truth table but am having a bit of difficulty with the Kmpas and logic diagrams for the BCD to 74210 encoder.

Any assistance would be appreciated.

It would be better, if you can show the expressions you have figured out so far, and I'll try to show you where you are going astray.
(that will also give me a chance to go dig up where i put my scratch paper for that problem... you're lucky i didn't throw that one away)

 

[Kenneth Mann]

The difficulty seems to have less to do with the problem itself than with working with Karnaugh Maps. Maybe one of us should give an introductory tutorial in using these (we would assume that basic logic is understood). I could do so (estimate four or five or so sections), if there is interest in it. The problems I see are two. First, the space allowed in this forum is only about 25K bytes for an attached file, and the maps I have take about 30 to 90K. Second, by the time it is done it would likely be too late for ALJ's assignment. In any case, if anyone knows how to input larger attachments, and if anyone is interested, I can show how "Reflective Karnaugh Maps work.

KM

 

[Ouabache]

The difficulty seems to have less to do with the problem itself than with working with Karnaugh Maps. Maybe one of us should give an introductory tutorial in using these (we would assume that basic logic is understood). I could do so (estimate four or five or so sections), if there is interest in it. The problems I see are two. First, the space allowed in this forum is only about 25K bytes for an attached file, and the maps I have take about 30 to 90K. Second, by the time it is done it would likely be too late for ALJ's assignment. In any case, if anyone knows how to input larger attachments, and if anyone is interested, I can show how "Reflective Karnaugh Maps work.

KM

Ken, perhaps you are right. Maybe you could post a K-map for one of the outputs as an example. It sounds like there would be space for one.

 

[MirrorM]

Hi

Im having trouble drawing the circuit in micro cap. Would someone please happy me with this or drop a few hints. Would it be correct in saying that I have to have 2 leds turn on for each of the outputs?

Ive also been told that this circuit can be build with 8 or 9 ics only, do you believe this to be correct.

Thanks

 

[weeds]

Can I simplify this any further

It would be better, if you can show the expressions you have figured out so far, and I'll try to show you where you are going astray.
(that will also give me a chance to go dig up where i put my scratch paper for that problem... you're lucky i didn't throw that away)

this is what I got for my output.can this be simplified any further.No use of exclusive gates.Do not tell the answer just hints

Thanks

P0=A'BC'D'+A'B'C'D+A'BCD+A'B'CD'

P1=AB'C'D'+A'B'D+A'C'D

P2=AB'C'D+A'B'C+A'CD'

P4=A'C'D'+A'BC'+A'BD'

P7=A'BCD+B'C'D'+AB'C'

 

[Ouabache]

Hi

Im having trouble drawing the circuit in micro cap. Would someone please happy me with this or drop a few hints. Would it be correct in saying that I have to have 2 leds turn on for each of the outputs?

Ive also been told that this circuit can be build with 8 or 9 ics only, do you believe this to be correct.

Thanks

I can't help with the first one, I don't have micro cap. You might ask weeds, I think he is familiar with that program.

Whether you can build this with 8 or 9 ICs, it depends on which ICs are available to you. For example some ICs have 4 gates/chip with 2 inputs/gate. Some have 3 gates/chip with 3 inputs/gate, and yet another has 2 gates/chip with 4 inputs/gate. You're lucky you haven't been told you can only use one type of gate (for example NAND). That was a spec I had to work with one time.

 

[MirrorM]

P0=A'BC'D'+A'B'C'D+A'BCD+A'B'CD'

P1=AB'C'D'+A'B'D+A'C'D

P2=AB'C'D+A'B'C+A'CD'

P4=A'C'D'+A'BC'+A'BD'

P7=A'BCD+B'C'D'+AB'C'[/QUOTE]


Ive tested these in micro cap and I not believe they are correct, have you tested them?

Which IC's did you use to create your design?

 

[MirrorM]

Ive just completed a working design using 8 AND gates and 1 OR gate plus 4 inverters. Do the Inverters count as ic's?

What did you use WEED?

 

[Ouabache]

this is what I got for my output. Can this be simplified any further.

P0=A'BC'D'+A'B'C'D+A'BCD+A'B'CD'
P1=AB'C'D'+A'B'D+A'C'D
P2=AB'C'D+A'B'C+A'CD'
P4=A'C'D'+A'BC'+A'BD'
P7=A'BCD+B'C'D'+AB'C'

They look good! For a morale boost, I compared these to mine and they are the same. I don't see any obvious way to simplify them further. The K-maps do a pretty nice job.

 

[Ouabache]

Ive tested these in micro cap and I not believe they are correct, have you tested them?

If you look at the earlier posts, you will see that Weeds successfully verified his equations with micro cap.

"Using micro cap I drew the circuit (logic) fed my inputs A,B,C and D and what I got as outputs (P7...) matched my Truth table.

Ive just completed a working design using 8 AND gates and 1 OR gate plus 4 inverters. Do the Inverters count as ic's?

Were you successful deriving your equations from your Kmaps?
How will you invert a signal without using an IC ??

 

[Kenneth Mann]

Your answers are correct, however, I'd like to note that the usual procedure is to put the A, B, C and D terms in the truth table with "A" in the low order position (to the right). This makes it easier to put it into an ordered/reflected K-Map. I have attached two truth tables (Example01) and the K-Maps and logic equations (Example02and Example03) for term "P7".

Note that the logic generated is different for the two cases, but both cases are correct (showing that there is more than one right answer – actually 24). They all give the same configuration of gates. It is easier, however with the standard arrangement of A, B, C and D, because in this order, the terms go easily into the reflected K-Map (You can probably see why).

Sorry for the ugly maps, but they they had to be drawn in under 25K each, which is not the most versatile. I also have better for these maps in Word (which looks better) and Pagemaker (which looks even better), but these result in large files. If anyone wants copies I'd be glad to send them. I can also show how the reflected K-Map is used. (The number of variables a map can handle is limited only by the size of the map that can be drawn.)

Note, also that the terms of the equations derived can be combined by grouping, however a quick examination showed no apparent advantages to that. (I'm not saying that something simpler cannot be found, just that I didn't readily see anything.)

KM
P.S: The arrangement you have now will take 10 ICs counting the inverter. If the inverted signals are already provided, the inverter can be omitted, leaving 9.

 

[Rev Prez]

This makes it easier to put it into an ordered/reflected K-Map.

That's an interesting way to set up a four input K-Map.

Rev Prez

 

[Kenneth Mann]

This approach will let you set-up a 10-input K-Map if you want to.

KM

 

[MirrorM]

If you look at the earlier posts, you will see that Weeds successfully verified his equations with micro cap.



Were you successful deriving your equations from your Kmaps?
How will you invert a signal without using an IC ??

Yes I successfully derived the equations from the kmaps. Thanks

 

[MirrorM]

Your answers are correct, however, I'd like to note that the usual procedure is to put the A, B, C and D terms in the truth table with "A" in the low order position (to the right). This makes it easier to put it into an ordered/reflected K-Map. I have attached two truth tables (Example01) and the K-Maps and logic equations (Example02and Example03) for term "P7".

Note that the logic generated is different for the two cases, but both cases are correct (showing that there is more than one right answer – actually 24). They all give the same configuration of gates. It is easier, however with the standard arrangement of A, B, C and D, because in this order, the terms go easily into the reflected K-Map (You can probably see why).

Sorry for the ugly maps, but they they had to be drawn in under 25K each, which is not the most versatile. I also have better for these maps in Word (which looks better) and Pagemaker (which looks even better), but these result in large files. If anyone wants copies I'd be glad to send them. I can also show how the reflected K-Map is used. (The number of variables a map can handle is limited only by the size of the map that can be drawn.)

Note, also that the terms of the equations derived can be combined by grouping, however a quick examination showed no apparent advantages to that. (I'm not saying that something simpler cannot be found, just that I didn't readily see anything.)

KM
P.S: The arrangement you have now will take 10 ICs counting the inverter. If the inverted signals are already provided, the inverter can be omitted, leaving 9.

Thanks heaps for the maps, they made me feel better about this project cause they were the same as I had.

I was able to configure the arrangement using twice as many IC's + inverters, then you have specificed (around 20), Would you please be able to show or tell me how the arrangement can be configured using only 9 or 10 ics.

The ics we have available are:

4 x 2 input AND gates in one IC
3 x 3 input AND gates in one IC
2 x 4 input AND gates in one IC
3 x 3 input OR gates in one IC
2 x 4 input OR gates in one IC
Hex inverter (6 hex inverters in one IC)


Thanks

 

[Rev Prez]

This approach will let you set-up a 10-input K-Map if you want to.

KM

How can you include more than four inputs in a K Map? I thought you had to use some other method?

 

[Kenneth Mann]

Procedure:

When you have a logic equation like:

ABC' + D'E'F' + G'HI

In this example, there are nine different input signals, some negated, some not. (In a "real world" example several signals would probably be repeated in the equation, however I chose separate ones just to illustrate that there is no implied relationship necessary between them.) It is called a "simple sum-of-products" (SSOP) equation. What we have here is three product (AND) terms which are then "summed" (OR). Each of the "product" terms goes to an AND gate; for example, for (D'E'F'), each of the signals (after they have been inverted in this case), would be sent to to an AND gate. Likewise for the other two ANDed terms in the equation. Once we have derived the three products for the equation, we then "sum" them (send the three and outputs, in this case, to an OR), and you're finished with this equation. All additional equations are handled in the same way. Here, we use three 3-input ANDs (one IC), and feed their outputs to a 3-input OR (1/3 IC).

Note (FYI) you could use basically the same procedure with a "simple-product-of-sums equation like:

(A' + B' + C)(D + E + F)(G + H' + I')

In this case, we first send each of the signals going into one of the "sum" (OR) terms (like A' + B' + C) to an OR gate, and then feed each of the OR gate outputs directly to an AND gate. Note that the same number (four) of gates is used in both cases, and, in fact, that these two equations are equivalent. This indicated that whatever you can do with a simple-sum-of-products (AND-OR) equation can also be done with a simple-product-of-sums (OR-AND) equation, and they are, in fact, equivalent. (Prove it to yourself by complementing one of the equations. Note, however that in real life the minimized values you get from a map may not be complements of each other.)

Also note, that what we did in the "simple-sum-of-products" (SSOP) case
(ANDs followed by an OR) can also be accomplished with NANDs followed by another NAND. Likewise, what we did in the "simple-product-of-sums" (SPOS) case (ORs followed by an AND), can also be accomplished with NORs followed by another NOR. With TTL, where NANDs were cheapest and easiest to make it was convenient to always design for the "simple-sum-of-products case. (With CMOS, it doesn't really matter.)

By the way, to map for the SPOS case, just solve the map for the "zeros" (this gives you the SSOP for the "zeros"), then find the complement (this gives you the SSOP). As an example, mapping for zeros in "P7", you get:

P7' = A'B + BD + B'C + AC'D'

Then complementing, you get:

P7 = (A + B')(B' + D')(B + C')(A' + C + D) Remember DeMorgan

Why don't you try this for all the P terms. You might even get something simpler than SSOP (and maybe not). In any case the try might be worth extra credit (along with the SPOS case).

KM

PS: Note, that if the product term leading to the sum term (in a "simple-sum-of-products" [SSOP] equation) is the same as the sum term in any other equation, then the same AND (or NAND for a NAND-NAND case) gate can be shared, thus saving the use of one gate. (Similarly for the SSOP case.)

 

[Kenneth Mann]

How can you include more than four inputs in a K Map? I thought you had to use some other method?

To show that I'd have to explain the 'reflected' K-Map. I'd be glad to do so, but I'll need to be able to transfer files (map drawings) a lot larger than allowed in this forum (especially if I have to use Acrobat; Word files can be a bit smaller). I can offer a short tutorial (5 - 8 sections) but I'll need a way to do it. Any suggestions.

KM

 

[MirrorM]

When you have a logic equation like:

ABC' + D'E'F' + G'HI

Here, we use three 3-input ANDs (one IC), and feed their outputs to a 3-input OR (1/3 IC).

So if you had a question on the number of IC's used, would the answer be 1 1/3 (three 3-input ANDs (one IC), and feed their outputs to a 3-input OR (1/3 IC)) or 2 IC's because is can't have 1/3 of an IC?( can you?)

 

[Kenneth Mann]

So if you had a question on the number of IC's used, would the answer be 1 1/3 (three 3-input ANDs (one IC), and feed their outputs to a 3-input OR (1/3 IC)) or 2 IC's because is can't have 1/3 of an IC?( can you?)

Obviously, you'd have to round the number up to the next larger value, but remember, that you have several such equations (five in your problem), and the other equations might also need some 3-input ORs. Thus say that all of the equations needed eleven 3-input ANDs and four 3-input ORs. In that case your total IC requirement for 3-input ANDs would be four and for 3-input ORs would be two. You use the fractional figures to count the number of ICs needed for each equation, then when you've added up the total for all of your equations, round the number up.

Even better, count the gates of each type needed for each equation, then
add these up, divide the total gate count needed for each gate type, by the number per IC, and round up.

KM

 

[Kenneth Mann]

Just for the exercise, I decided to try this problem, using the SPOS (Simple-Product-Of-Sums) approach) and this time, got nine/ten ICs. (Using the SSOP approach I also got, as I recall, ten ICs, counting inverters.) To go back over the process, what I did was the following, this time looking for the SPOS answer:

First I mapped each of the five desired output signals, but this time for the "zeros". (You should check it in case I made an error.) What I got was the following, in the case of P7:

P7' = A'B'C' + B'C'D + ABCD'

Then I combined terms to get:

P7' = (A' + D)B'C' + ABCD'

Then, DeMorgan was applied to get P7', to get what follows:

P7 = (AD' + B + C)(A' + B' + C' + D)

This 'term' requires:

2' 2-input AND
1, 3-input OR
1, 4-input OR

Doing the same for the other four terms got a total requirement for:

1 4 input OR = 1 IC
1 3 input OR = 1 IC
12 2 input OR = 3 IC
7 2 input AND = 2 IC
4 3 input AND = 2 IC
4 Inverter = 1 IC

Total = 10 IC

It can be noted here, though that both the 3-input OR and the 4-input OR functions can be handled by a single dual-4-input OR IC. (Where a 3-input OR is needed, one of the inputs can simply be grounded.) This would leave a requirement for nine ICs.

It might be worth something extra if you work the problem out this way in addition to the SSOP way.

KM