About microprocessor 8085: state signals?

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Discussion Overview

The discussion revolves around the state signals S0, S1, and IO/M* of the 8085AH microprocessor, focusing on their roles during different machine cycles such as OpCode Fetch, read, write, and halt. Participants explore the utility and functionality of these signals in the context of instruction decoding and potential applications in hardware debugging.

Discussion Character

  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant inquires about the function of S0 and S1 signals and their connection to the instruction decoder in determining machine cycle status.
  • Another participant provides a table correlating the states of S0 and S1 with specific operations: (0,0) for halt, (0,1) for read, (1,0) for write, and (1,1) for fetch.
  • A participant expresses uncertainty about the usefulness of S0 and S1, suggesting that the processor determines the operation type before updating these signals.
  • It is proposed that S0 and S1 could be utilized to create a visual indicator, such as a "blinking light" front panel, to display the processor's activity.
  • Another suggestion involves using S0 and S1 for a hardware debugger that could allow control over the processor based on observed signal combinations.

Areas of Agreement / Disagreement

Participants exhibit uncertainty regarding the practical utility of S0 and S1 signals, with some suggesting potential applications while others question their necessity. No consensus is reached on their overall usefulness or implementation.

Contextual Notes

Participants note that S0 and S1 are updated prior to memory operations, but the implications of this timing and their integration with other signals remain unresolved.

ilconformista
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Hello everyone! Could anyone explain to me the following: The 8085AH has 3 state signals: S0, S1 and IO/M*. S0 and S1 provide different type of machine cycles depending on their status.

For example if the machine cycle is OpCode Fetch, we will get: S1=S0=1 and IO/M*=0. I don't get it though, what do the S1 and S0 signals actually do? I believe the processor decides their status with the help of the instruction decoder, and then what happens? They don't seem to connect to anything!

Thank you for your time.
 

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Code:
s0 s1
 0  0  halt
 0  1  read
 1  0  write
 1  1  fetch

Link to pdf file:

http://staff.neu.edu.tr/~kuyar/301/ch3.pdf
 
Last edited by a moderator:
rcgldr, thanks four your answer! However I still can't think of any way that these signals are useful. The processor decides first if it's halt, read, write or fetch (by decoding the instruction) and THEN updates the states of S0 and S1. Am I right?
 
ilconformista said:
rcgldr, thanks four your answer! However I still can't think of any way that these signals are useful. The processor decides first if it's halt, read, write or fetch (by decoding the instruction) and THEN updates the states of S0 and S1. Am I right?
S0 and S1 don't have to be used, since there are already other signals for read and write. Fetch will occur when reading instructions. If a program was coded carefully, fetch could be used to address some type of rom instead of main memory, effectively extending the address space. S0 and S1 are updated before a memory operation takes place.
 
You could use S0 and S1 and some of the other status lines to create a "blinking light" front panel that would show what the processor is doing. It might be feasible to single step the processor one button press at a time and this would let you watch the status signals, address lines, data lines, etc.

You could use S0 and S1 to build a hardware debugger that would allow you to stop the processor and grab control with a particular combination was observed.
 

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