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twoski
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Homework Statement
Consider a cache memory system having the following characteristics :
- 512 Mbytes of main memory.
- Word size of 4 bytes.
- Cache size of 512 Kbytes.
- Line size of 8 bytes.
(a) Determine the address formats for (i) direct, (ii) associative, and (iii) two-way set associative mappings.
(b) For each of the following situations, explain whether programmed I/O, interrupt driven I/O, or DMA should be used.
(i) Transfer of a large block of data.
(ii) Transfer of a few bytes.
(iii) Transfer of a few bytes within a given time limit.
The Attempt at a Solution
The example our professor gave us doesn't explain anything so I'm not sure how to proceed.
Here's his example:
Cache size: 128 words
Line size: 8 words
Main memory: 16 kbytes
Number of memory blocks: 2k
Therefore, the Direct Address Format is 7 tag bits, 4 line bits and 3 word bits.
I have no clue how that conclusion was reached. How is it decided that there are 14 bits in an address? And how are the number of tag bits, etc. decided?