Can you put more light on DFG-FET?

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Dual-floating gate field effect transistors (DFG-FETs) represent a potential advancement in memory technology, combining features of DRAM and Flash cells. The use of high-k dielectrics, such as HfO2, enhances MOS gain but presents challenges, including reliability and endurance limits due to oxide damage during write-erase cycles. Current limitations in CMOS scaling suggest that Moore's Law may be nearing its end, necessitating alternative technologies. Despite theoretical advantages, practical issues with HfO2 and concerns about material scarcity complicate DFG-FET implementation. Overall, while DFG-FETs show promise, significant hurdles remain before they can be widely adopted.
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Dual-floating gate field effect transistors or DFG-FETs may be the future of memory elements.
Have you heard about it?
http://www.bit-tech.net/news/hardware/2011/01/25/dfg-fet-memory-tech/1"
 
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pairofstrings said:
Dual-floating gate field effect transistors or DFG-FETs may be the future of memory elements.
Have you heard about it?
http://www.bit-tech.net/news/hardware/2011/01/25/dfg-fet-memory-tech/1"

Basically it's a high-k dielectric DRAM + Flash cell. Not actually all the different from a conventional Flash cell but the high-k alters the MOS gain in particular ways. It has two floating gates instead of one - one is just a Flash-like NVM cell while the other is a DRAM-like capacitor plate. I can see strengths and weaknesses with this.

It has no more chance (or less change) than any other ng-NVM technology, of which there are many (e.g. FRAM, MRAM, PRAM, etc.).
 
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jsgruszynski, how is this high K different from other gate materials.
k is the dielectric constant?
 
HfO2 is the typical material. Higher dielectric constant which increases the MOS couple to the channel. High-k is the basis of current next process shrink for sub-30nm CMOS.

Basically you "must" (according to classical Moore's Law scaling rules) shrink oxide thickness along with channel length, and "oops", direct tunneling kicks in strongly with this shrink making the gate current a significant fraction of the drain current. So we have to back off on gate shrink and the other alternative in the MOS device equation for increasing Cox is increasing k. Basically we can't shrink gate oxide anymore. Moore's Law for CMOS is close to its end. There are other technologies in the line up but none are quite mature yet.

The problem with HfO2 is that there are issues with it practically: Si from the channel tends to migrate into the HfO2 to form SiO2 which takes you back to the original problem. Creating a barrier layer also defeats the purpose because any barrier layer drops the dielectric constant and HfO2 is one of the highest k practical dielectrics in the periodic table (it's high-k and low-hysteresis - most other high-k materials have high-hysteresis). And the effectiveness of higher k is inversely proportional to the distance to the channel (closest is best).

The DRAM part is likely a high-k capacitor also (that's what regular DRAM are already moving to) with a related dielectric could be HfSiO.

The biggest issue will be reliability - how long will a device maintain its normal function. Dielectrics are not supposed to conduct current but that exactly what you must do in a write or erase cycle. So you create damage with each write and erase operations. This is where the "endurance" spec of any floating gate technology comes in - it's the number of write-erase cycles you can perform before you can't sense a 0 or 1 any more. All Flash (or EPROM OR EEPROM) die eventually from this oxide damage. The risk is that even the DRAM portion could be compromised by Flash write-erase currents.

And it's a surprisingly few # of cycles before you hit endurance limits. 105-107 sounds large until you consider how many cycles you can hit if you were to write-erase at-speed with a modern microprocessor. But "fortunately", Flash write-erase cycles are very slow so that limits the "enthusiasm" that would cause a problem. Even so, the limits are enough of an issue with slow cycles that SDD controllers and SSD file systems had to be invented to make SSD practical - basically these are "write-erase cycle avoidance" systems.

For NAND flash, at least both are Fowler-Nordheim tunneling rather than FN tunneling plus avalanche current, which is very damaging. But the problems rearing their heads with just regular CMOS high-k dielectrics are suggesting that getting even FN currents through HfO2 won't be a walk in the park. It might not even be possible. We don't know yet.

There's also a risk of "Peak Hafnium": it's not the most common substance on Earth and there is concern we'll use all reserves of it quite quickly.

But, in theory, HfO2 should work great. And eventually it probably/maybe will. Just not yet. The referenced link does lead back to academia so no surprises that it's wildly optimistic and theoretical rather than practical. But they certainly have their university PR machine running just as slimy as any corporation. Sad but to be expected - US universities are more corporations now than academic institutions.

I should also point out the idea isn't very new. Everyone in the industry has noted the similarities they claim are so insightful more than a decade ago. The chances for a convergent evolution were pretty clear long ago but it's the details that get you.
 
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