Cascaded op-amp stages and saturation of final stage

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SUMMARY

The forum discussion centers on the design and simulation of a three-stage cascaded amplifier using op-amps, specifically the OP07 and TL081 models. The user initially aimed for a gain of 30 per stage with an input voltage of 1V, resulting in an unrealistic output voltage of 27,000V. Participants emphasized the importance of using appropriate power supply levels, calculating total gain based on desired input and output voltages, and implementing high-pass filter capacitors to manage DC offset. The consensus is that the design must be revised to ensure the input voltage is significantly lower, ideally around 0.1mV, to avoid saturation and achieve the desired gain.

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  • Understanding of op-amp configurations and limitations, specifically for OP07 and TL081.
  • Knowledge of gain calculations in amplifier circuits.
  • Familiarity with high-pass filter design and its role in blocking DC offset.
  • Experience with circuit simulation tools like Proteus.
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  • Learn about op-amp power supply requirements and output swing limitations.
  • Research high-pass filter design principles and how to calculate cut-off frequencies.
  • Explore circuit simulation techniques to validate amplifier designs before physical implementation.
  • Study gain staging in audio and signal processing applications to optimize amplifier performance.
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Electronics students, circuit designers, and engineers working on amplifier design and simulation, particularly those focused on op-amp applications and signal processing.

  • #31
CWatters said:
I do not understand why you have these two capacitors...

View attachment 222587
I used these capacitors to reduce the DC offset voltage.
 
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  • #32
CWatters said:
Here is my version of the circuit. My version amplifies AC only. If your source V1 is DC you need a different circuit.

I have not shown the power supply.

1) Input voltage: 0.1mV AC
2) Output voltage: 2.7V AC
3)Total gain required:2.7/(0.1*10^-3)=27000
4) I am using three stages each of gain of 30

View attachment 222592

The gain of the first stage is set by R2 and R1. Stage 2 and 3 are the same.

Capacitor C1 and R3 form a "high pass" circuit. This has a "cut-off frequency" of about 160Hz. Same for C2, R6, and C3, R9. This blocks any DC offset.

If you need a different cut-off frequency you can change C1, C2, and C3.

See also http://sim.okawa-denshi.jp/en/CRtool.php

Here is the output from the simulator. It is the frequency response for the output of stage 3 (Net1008).

View attachment 222595

The output (above the cut off frequency) is 2.9V
Tq, for the work done. Cant, we use DC input voltage and get the voltage, since while doing practically we prefer DC voltage to AC voltage. Can Even we use 10mV of input to draw the gain? Give me a solution.
 
  • #33
jSwathi said:
Tq, for the work done. Cant, we use DC input voltage and get the voltage, since while doing practically we prefer DC voltage to AC voltage. Can Even we use 10mV of input to draw the gain? Give me a solution.
If the source is DC you must make these changes to my circuit.

1) replace the capacitors with a wire link.

2) add a variable resistor to each op-amp to remove the DC offset voltage. See the date sheet for how to do this. The offset voltage for the OP07 can be 75uV so if you do not do this the output could be 2V even with 0V input. 75uV * 27000=2V.

You cannot have an input of 10mV and a gain of 27000 because the output voltage would be 10mV * 27000=270v. This is too high. If the input must be 10mV then you must reduce the gain. I have explained this already. The maximum recommended power supply you can use is 15V. If the power supply is 15V then the maximum output of stage 3 is 12V. The maximum overall gain is 12V/10mV=1200. So if the input V1 is 10mV the maximum overall gain possible is 1200. So the maximum gain per stage is 10.6. You could use 12*10*10.
 
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