Cascaded op-amp stages and saturation of final stage

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Discussion Overview

The discussion revolves around the design and simulation of a three-stage cascading amplifier using op-amps. Participants explore issues related to gain, saturation, and the necessity of capacitors in the circuit. The conversation includes technical details about voltage levels, power supply requirements, and the implications of using different input voltages.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Homework-related
  • Mathematical reasoning

Main Points Raised

  • One participant states their goal is to achieve a gain of 30 for each stage with an input voltage of 1V, leading to concerns about output saturation at 15V.
  • Another participant notes that the output swing of op-amps is limited by the power supply, suggesting saturation could occur if the supply voltage is insufficient.
  • Several participants discuss the implications of DC offset in high-gain configurations and the potential need for high-pass filter capacitors between stages to mitigate this issue.
  • One participant questions the feasibility of achieving a gain of 27,000 with the proposed design, highlighting the unrealistic output voltage that would result.
  • Another participant suggests recalculating the input voltage to achieve the desired gain, emphasizing the importance of knowing both input and output voltages for gain calculations.
  • Some participants provide links to resources and datasheets for op-amps, discussing the limitations of specific models like the TL081 and OP07 regarding output swing and power supply requirements.
  • There is a suggestion to reconsider the design approach, emphasizing a structured method for determining input, output, and total gain requirements.
  • One participant expresses gratitude for the support received and shares an updated design for further feedback.

Areas of Agreement / Disagreement

Participants express differing views on the design approach and the feasibility of achieving the desired gain. There is no consensus on the correct method for calculating gain or the necessity of capacitors in the circuit.

Contextual Notes

Participants highlight limitations related to the power supply voltage and the output swing of op-amps, as well as the potential for DC offset to affect high-gain stages. The discussion reflects various assumptions about circuit design that may not be universally applicable.

Who May Find This Useful

Readers interested in amplifier design, op-amp configurations, and circuit simulation may find this discussion relevant, particularly those working on similar homework or project-based tasks in electronics.

  • #31
CWatters said:
I do not understand why you have these two capacitors...

View attachment 222587
I used these capacitors to reduce the DC offset voltage.
 
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  • #32
CWatters said:
Here is my version of the circuit. My version amplifies AC only. If your source V1 is DC you need a different circuit.

I have not shown the power supply.

1) Input voltage: 0.1mV AC
2) Output voltage: 2.7V AC
3)Total gain required:2.7/(0.1*10^-3)=27000
4) I am using three stages each of gain of 30

View attachment 222592

The gain of the first stage is set by R2 and R1. Stage 2 and 3 are the same.

Capacitor C1 and R3 form a "high pass" circuit. This has a "cut-off frequency" of about 160Hz. Same for C2, R6, and C3, R9. This blocks any DC offset.

If you need a different cut-off frequency you can change C1, C2, and C3.

See also http://sim.okawa-denshi.jp/en/CRtool.php

Here is the output from the simulator. It is the frequency response for the output of stage 3 (Net1008).

View attachment 222595

The output (above the cut off frequency) is 2.9V
Tq, for the work done. Cant, we use DC input voltage and get the voltage, since while doing practically we prefer DC voltage to AC voltage. Can Even we use 10mV of input to draw the gain? Give me a solution.
 
  • #33
jSwathi said:
Tq, for the work done. Cant, we use DC input voltage and get the voltage, since while doing practically we prefer DC voltage to AC voltage. Can Even we use 10mV of input to draw the gain? Give me a solution.
If the source is DC you must make these changes to my circuit.

1) replace the capacitors with a wire link.

2) add a variable resistor to each op-amp to remove the DC offset voltage. See the date sheet for how to do this. The offset voltage for the OP07 can be 75uV so if you do not do this the output could be 2V even with 0V input. 75uV * 27000=2V.

You cannot have an input of 10mV and a gain of 27000 because the output voltage would be 10mV * 27000=270v. This is too high. If the input must be 10mV then you must reduce the gain. I have explained this already. The maximum recommended power supply you can use is 15V. If the power supply is 15V then the maximum output of stage 3 is 12V. The maximum overall gain is 12V/10mV=1200. So if the input V1 is 10mV the maximum overall gain possible is 1200. So the maximum gain per stage is 10.6. You could use 12*10*10.
 
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