Charge Pumps -Query - Ripple Vs Switching Frequency

[shaikss]

Hi Folks,

I tried designing a Dickson's charge pump.
Here are the below observations:

For a voltage doubler:

When W=240nm, charge pump capacitance= load capacitance= 1p F, load resistance= 10M ohm, Switching frequency=500k Hz, Vin=2V

Results:

Vout= 4.3772V, settling time= 50u s (4.3366V).
Here settling time refers to time at which output have a constant value.

1. I tried to increase the switching frequency to 500M Hz, peak of output voltage ripple is slightly decreasing.

2. Decreasing the load resistance resulted in the increase of output ripple.
3. When I try to lower the switching frequency, the load resistance required to have reasonable output is increasing.

4. With constant load resistance: if load capacitance increases then settling time increases and ripple decreases but output is same.
5. With constant load capacitance: if load resistance decreases then output decreases and ripple increases but settling time is same.


6. with an increase in the charge pump capacitance, settling time and output voltage decreases.

7. With an increase in 'w' of nmos : best results are coming for 240n M for all the frequencies. I assumed that the with the increase in 'W', best results will come. But best results are coming for 240nm width.

Can you explain me the reason behind all the seven observations?

Thanks!

 

[DragonPetter]

Hi Folks,

I tried designing a Dickson's charge pump.
Here are the below observations:

For a voltage doubler:

When W=240nm, charge pump capacitance= load capacitance= 1p F, load resistance= 10M ohm, Switching frequency=500k Hz, Vin=2V

Results:

Vout= 4.3772V, settling time= 50u s (4.3366V).
Here settling time refers to time at which output have a constant value.

1. I tried to increase the switching frequency to 500M Hz, peak of output voltage ripple is slightly decreasing.

By switching the capacitors faster, you are reducing their "switching resistance" which can be derived by the change in charge over the switching time (current). So as the switching time decreases, the change in charge over a given amount of time increases such that its resistance is dropping. This "Switching resistance" is in series with the charge pump capacitors and so they form an RC circuit. As the switching frequency increases, this RC time constant decreases and so more current is able to be supplied to the load resistor, and thus less ripple occurs.

2. Decreasing the load resistance resulted in the increase of output ripple.

By decreasing the load resistance, you need more current to give the same voltage output, and so you're discharging and charging your charge pump capacitors a lot more now each cycle. This means their voltage is changing more each cycle and so your output ripple is increased.

3. When I try to lower the switching frequency, the load resistance required to have reasonable output is increasing.

This is just sort of a combination of my answers for 1 and 2. Lowering the switching frequency reduces the amount of current you can supply to your charge pump capacitors, and so you need to increase your load resistance so that you require less current drawn from the capacitors.

4. With constant load resistance: if load capacitance increases then settling time increases and ripple decreases but output is same.

You have to just consider a load capacitance as a capacitor in series with your charge pump, and your charge pump has a series resistance determined by the switching frequency. Increasing C increases the time constant.

5. With constant load capacitance: if load resistance decreases then output decreases and ripple increases but settling time is same.

Again, the load resistor is increasing current draw, which means the charging capacitors need to fill/discharge more current each cycle which causes more ripple. The output decreases most likely because the charge pump capacitors are drained so much each cycle that they never fully charge and the load capacitor is acting like an "impedance voltage divider" with the charge capacitors.

6. with an increase in the charge pump capacitance, settling time and output voltage decreases.

By increasing the charge pump capacitance, you are able to supply more current to the load. Output voltage may increase because your are switching so fast and your load is drawing the current before the charge pump capacitors can ever charge to full voltage.

7. With an increase in 'w' of nmos : best results are coming for 240n M for all the frequencies. I assumed that the with the increase in 'W', best results will come. But best results are coming for 240nm width.

I don't have time to think about this question, but my own experience with FETs in the charge pump is that there is a maximum practical frequency where you stop gaining current throughput with frequency increase, and my thoughts are that this is limited by the power disipation of the FET. Once you reach a certain frequency, your FET is dissipating any extra current you can supply when it is in the triode mode during its imperfect switches. My only hint/thought is that your increase in W will decrease the Rds which allows for more current throughput for your FET, but it will also increase its capacitance which lowers the charging voltage for your charge pump capacitors since they're in series. I know this doesn't anwer your question, but it is the only relevant information I can give you quickly about FETs in charge pumps. I'd have to study the question a bit to give you a better answer.

 

[shaikss]

Thanks Dragon petter. Can you please give your thought on the last query.
Increasing the width of the MOS increases the current and so the voltage.
But I am not figuring out the reason why the increase in the width of MOS is limited the frequency? What are the different reasons for this behaviour?

What should be the maximum limiting frequency?

How are the parameters like frequency, capacitance , load related to the number of stages of Charge Pump used?

Generally how much should be the settling time? If I am sending a RF signal to the receiver part at 865MHz and that ac signal is rectified and then given to ChargePump. Based on this criterion, what should be the settling time for effective operation of the IC?