Engineering CMOS inverter circuit, spike in simulation

[SMOF]

Hello,

I am hoping someone can give me a little bit of help.

I have been simulating a CMOS inverter circuit. When I add in a pulse source at the input, and simulate it, I get an output which has a bit of a spikle on the transition.

I am hoping someone can help my understand why this is here? I have attached a picture of the simulated output.

Now, when I had in a capacitor at the load, the spike is far less pronounced, but I am sure that is just because of the smoothing effects of the cap.

Also, I want to put this information into a report, so I would actullay like to understand what is going on, rather than just been told it is because of x thing.

I hope that doesn;t sound rude of me, I really don't mean to be.

Many thanks in advance.

Seán

 

[NascentOxygen]

For an input that rises from 0 to 1, the output momentarily rises higher than the supply rail, before dropping to 0? Sounds like capacitive coupling of some of the input to the output; beyond that I can't say. Do you see a similar negative spike during the reverse transition?

Does that output spike appear to be limited at one diode drop above the supply rail?

 

[SMOF]

Sounds like capacitive coupling of some of the input to the output

Hello.

Yes, that was it. I was able to get speaking to one of my lecturers, and he said that, basically, due to capacitive effects and what have you, an initial 'spike' at the input will take time to fully travel from the input to the output, so this causes the bit of distortion.

Seán