Assume you have a symmetrical clock at 100MHz. Design a logic circuit with four outputs of clocks at 100MHz, 50MHz, 25MHz, and 12.5MHz. The logic circuit should have 2 inputs to select output clock rate.
The Attempt at a Solution
For starters, my teacher does a poor job lecturing and he assigned this problem on this week's assignment, and we won't have another class period before we turn this HW in. We hardly went over clocks, in this sense. Is there any words of wisdom from anyone to lead me in the right direction? Any links that may be helpful for me to solve this problem? Thank you to all who may offer assistance!