# Design digital logic clocks with given frequencies

• satchmo05
I totally understand where you're coming from, haha. A lot of this trouble came from the design, and which type of clock to use. I remember going over stuff like this in 140, but that was what, nearly 2 years ago now. Thanks for the help. You need any help on the assignment? I have the rest done I think.Yeah. I assume number 4 is in the manual, fortunately. Number 6 should be similar. So, I suppose help on 5 and 7 (despite the incorrect numbering in the hw) would be much appreciated!Alright, no worries. Don't take my word for it, because I really do not know if I have the right implementation.f

## Homework Statement

Assume you have a symmetrical clock at 100MHz. Design a logic circuit with four outputs of clocks at 100MHz, 50MHz, 25MHz, and 12.5MHz. The logic circuit should have 2 inputs to select output clock rate.

N/A

## The Attempt at a Solution

For starters, my teacher does a poor job lecturing and he assigned this problem on this week's assignment, and we won't have another class period before we turn this HW in. We hardly went over clocks, in this sense. Is there any words of wisdom from anyone to lead me in the right direction? Any links that may be helpful for me to solve this problem? Thank you to all who may offer assistance!

Hey, if you're talking about Minden, then I am in your class. I agree that there aren't many resources to try and solve this problem. I'm assuming we have to use D-Flip Flops--and probably four of them, the first outputs to 100MHz, and another line runs to a second which outputs at 50MHz, etc. The trouble is the overall design of the circuit.

I totally understand where you're coming from, haha. A lot of this trouble came from the design, and which type of clock to use. I remember going over stuff like this in 140, but that was what, nearly 2 years ago now. Thanks for the help. You need any help on the assignment? I have the rest done I think.

Yeah. I assume number 4 is in the manual, fortunately. Number 6 should be similar. So, I suppose help on 5 and 7 (despite the incorrect numbering in the hw) would be much appreciated!

Alright, no worries. Don't take my word for it, because I really do not know if I have the right implementation. What I have done definitely makes sense to me, but you never know... He kinda went over #5 in class - he mentioned that there are 64k counts in the ECT block diagram on the website (can also be found there). So basically, what I received for my answer was: given interval * # of ECT counts = delta(T), which is what you're looking for. For number 7, wiki "Nyquist-Shannon Sampling Theorem." I say this because we probably will not go over it in class and it may be helpful depending on your major.

Out of curiousity, what were your steps for problems #2 (resistor problem) and problem #6 (baud rate problem). Let me know when you can. Thanks!

Oh, what was your reasoning for choosing D-flip-flops? And how would you design this "outputting to 100MHz, etc.?"

Have you studied JK flip-flops and their 'toggle' operation? That is a very common way of implementing a frequency divider.

## Homework Statement

Assume you have a symmetrical clock at 100MHz. Design a logic circuit with four outputs of clocks at 100MHz, 50MHz, 25MHz, and 12.5MHz. The logic circuit should have 2 inputs to select output clock rate.

N/A

## The Attempt at a Solution

For starters, my teacher does a poor job lecturing and he assigned this problem on this week's assignment, and we won't have another class period before we turn this HW in. We hardly went over clocks, in this sense. Is there any words of wisdom from anyone to lead me in the right direction? Any links that may be helpful for me to solve this problem? Thank you to all who may offer assistance!

BTW, I'm pretty sure that to get full credit, you will need to ensure glitch-free switching between the output frequencies. That complicates the design somewhat, but is critical in the real world. So when you switch from 100MHz to 25MHz, for example, you only do it on an even 25MHz clock boundary...

BTW, to provide this glitch-free switching, you will also need to do something with the input signals that select the output frequency. Quiz question -- when you have an asynchronous signal coming into a synchronous clocked domain, what do you have to do with that signal? How do you do it? Why do you have to do it?