Design ultralow power, narrow band ADC

AI Thread Summary
The discussion focuses on designing an ultralow power, narrow band ADC with specifications of a 20MHz input frequency, 20MHz bandwidth, an ENOB greater than 4, and power consumption under 1mW. Suggestions include considering a flash ADC design due to the low bit requirement, which would only need 15 comparators, although this may be slow. The challenge of achieving such low power consumption is highlighted, with existing commercial units typically consuming more than the desired limit. Participants recommend exploring specific IEEE papers and resources for potential solutions and architectures. The conversation emphasizes the need for innovative design approaches to meet these stringent specifications.
anhnha
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Hi,
I want to design an ADC with these specifications:
Fin = 20MHz
BW= 20MHz
ENOB > 4
Power consumption P < 1mW
Could anyone suggest me some ADC for this kind? I have searched a lot in
IEEE but there are only two ADC with SAR ADC and time-interleaved ADC.
The ultralow power consumption makes it hard for me to find a
architecture. I have little experience about this. Kindly help me.
 
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You like a challenge don't you !

To convert a 20MHz signal Nyquist says you will need one converter at 40Msps or two at 20Msps.
The best commercial unit would be 8 bits at about 50mW. But you only want 4 bits.

A resistive divider with 15 comparators might be possible but 15 comparators at 40MHz (= 25ns) will draw about 15ma at 3 volts = 45mW. You might minimise the power slightly by using 15 AC coupled single transistors as your comparators. A sample pulse switches AC inputs from reference to signal at 40Msps.

Maybe some knowledge of your signal characteristics could reduce power by pre-processing. Can you tell me how the signal is modulated ?

Take a look at;
http://www.ti.com/lsds/ti/analog/dataconverters/data_converter.page
http://www.linear.com/products/Analog-to-Digital_Converters_(ADC)
http://www.linear.com/products/Comparators
 
anhnha said:
Hi,
I want to design an ADC with these specifications:
Fin = 20MHz
BW= 20MHz
ENOB > 4
Power consumption P < 1mW
Could anyone suggest me some ADC for this kind? I have searched a lot in
IEEE but there are only two ADC with SAR ADC and time-interleaved ADC.
The ultralow power consumption makes it hard for me to find a
architecture. I have little experience about this. Kindly help me.

By design an ADC do you mean design an IC? If so, you didn't look that hard in IEEE.

Harpe, P.J.A., Zhou, C., Bi, Y., Meijs, N.P. van der, Wang, X., Philips, K.J.P., Dolmans, G. & Groot, H. de (2011). A 26μ W 8 bit 10 MS/s asynchronous SAR ADC for low energy radios. IEEE Journal of Solid-State Circuits, 46(7), 1585-1595.

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05771068

Reduce the 8-bits to 4 and you can get the power no problem.

For a four-bit ADC though, maybe a straight flash is the way to go since you only need 15 comparators. Depends on the process you're using, of course.
 
This is slow but includes discussion of different methods including switched capacitors.
Very Low Power SAR ADC
 
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