Divide 180MHz Xtal Oscillator - Homebrew Design

[waht]

I need to divide 180 MHz from an xtal oscillator by 5 or 4. This will be like a homebrew design, so you guys know what prescaler to use? I would preffer to divide by 5, but if it turns out it's easier to divide by 4 I will take that route.

I was thinking to use the JK flip flop, but the F series goes up to like 120 MHz I think.

 

[berkeman]

That's pretty dang fast. Is the 180MHz signal a sine wave or square wave? Do you have a pointer to the datasheet for the oscillator? What is the output impedance and amplitude of the oscillator? What do you want the final signal to be? Sine, square, amplitude, source impedance, etc.?

 

[waht]

I made a quick sketch of what I'm doing.

180 MHz comes from a 7th overtone of a crystal oscillator. (sine wave)

Basically I have to generate a few frequencies from 180 MHz. By dividing it by 5 I would probably get a square wave, then filter it out to a sine wave. Frequency mulipliers are another nightmare I will worry later.

 

[berkeman]

Are you also doing the upconversion part to 2GHz?

What is the amplitude and source impedance for the oscillator output?

 

[waht]

the oscillator is buffered by a common emitter transistor amp. I can tap the output from the collector or the emitter for a lower impedance if necesary. I think that should be able to drive a logic circuit.

It either case it will me more than 50 ohms.

Some of these frequencies if it works, will be used to downconvert 3.2 GHz with 3 mixer stages, down to 4 MHz where variable bandwidth can be easily achieved.

 

[berkeman]

Well, ECL logic comes to mind as a possibility. I have never used it or any other differential signalling logic, but I think you will need to use one of the fast logic families mentioned in this article:

http://www.national.com/nationaledge/may03/article.html

You will also need to be careful with the layout of your signal traces and terminations. Hopefully ECL - LVDS - CML will meet your needs.

I'll also ping chroot to see if he can stop by an look at your question.

 

[chroot]

How about using a fully-analog PLL, followed by an ECL sine-to-square converter? 180 MHz would be a non-issue with that.

I would not even attempt to do the frequency division with flip-flops in discrete packages at such frequencies.

- Warren

 

[NoTime]

IIRC some of the prescaler chips used in frequency counters would do divide by 2 + divide by 5.
Usually set up for divide by 10 but the sections were independent.
They work to the 1+ Ghz range.

 

[chroot]

...And they're expensive!

The big problem with dividing down with flops is that you greatly increase jitter with each flop. (Of course, a divide by four is not all that big of a deal). A PLL won't have that problem, and they're cheap and easily available. You can make a communications-grade square wave synthesizer out of nothing more than a good analog PLL and an ECL inverter to square it up.

- Warren

 

[waht]

Thanks for the insights, ECL is an intersting topic. I've seen schematics of various frequency synthesizers and it's intersting how they generate different reference frequencies from the main over controlled oscillator. Multiply this by that, then divide, and multiply again, reference this to that. I wanted to at least follow the name architecture in my little project here.

I guess for now I will work on a pll.

 

[chroot]

You can buy many, many off-the-shelf PLL ICs that will work perfectly for your application -- I hope you don't mean you're going to try to build your own!

- Warrens