Electronic packaging cost / price

  • Thread starter Thread starter slibon
  • Start date Start date
  • Tags Tags
    Electronic
AI Thread Summary
Recent discussions on electronic packaging costs highlight a focus on low-cost packages like SOT23 and low I/O PLCC. Studies indicate that the number of pins significantly influences overall costs, with potential savings from omitting lead frames in BGA packages. However, high defect rates can negate these cost advantages if manufacturing processes are not optimized. Additionally, there is interest in the market for cheap LEDs and components in these packaging forms. Overall, thorough research and understanding of these factors are essential for cost-effective electronic packaging solutions.
slibon
Messages
1
Reaction score
0
Hello,

I am looking for recent info/studies on electronic packaging costs.
I focus on the extreme cheap type of packages (e.g. SOT23).
In general it nails it down to low I/O PLCC.
A study on components sold in this type of package form is interesting too.
Story on cheap LEDs interst me too.

Regards
 
Engineering news on Phys.org
slibon said:
Hello,

I am looking for recent info/studies on electronic packaging costs.
I focus on the extreme cheap type of packages (e.g. SOT23).
In general it nails it down to low I/O PLCC.
A study on components sold in this type of package form is interesting too.
Story on cheap LEDs interst me too.

Regards

I googled your term, studies on electronic packaging costs, and got lots of good hits:

http://www.google.com/search?source...1US302&q=studies+on+eletronic+packaging+costs

Google is your friend. Welcome to the PF, BTW.
 
I don't know if anyone makes it open knowledge, but cost of silicon + IP aside, the number of pins dominates. Of course, you can get discounts by leaving out the lead frame (BGA), but if your process isn't gloriously perfect, the defect rate will erase the BOM cost advantage.
 
Very basic question. Consider a 3-terminal device with terminals say A,B,C. Kirchhoff Current Law (KCL) and Kirchhoff Voltage Law (KVL) establish two relationships between the 3 currents entering the terminals and the 3 terminal's voltage pairs respectively. So we have 2 equations in 6 unknowns. To proceed further we need two more (independent) equations in order to solve the circuit the 3-terminal device is connected to (basically one treats such a device as an unbalanced two-port...
suppose you have two capacitors with a 0.1 Farad value and 12 VDC rating. label these as A and B. label the terminals of each as 1 and 2. you also have a voltmeter with a 40 volt linear range for DC. you also have a 9 volt DC power supply fed by mains. you charge each capacitor to 9 volts with terminal 1 being - (negative) and terminal 2 being + (positive). you connect the voltmeter to terminal A2 and to terminal B1. does it read any voltage? can - of one capacitor discharge + of the...
Thread 'Weird near-field phenomenon I get in my EM simulation'
I recently made a basic simulation of wire antennas and I am not sure if the near field in my simulation is modeled correctly. One of the things that worry me is the fact that sometimes I see in my simulation "movements" in the near field that seems to be faster than the speed of wave propagation I defined (the speed of light in the simulation). Specifically I see "nodes" of low amplitude in the E field that are quickly "emitted" from the antenna and then slow down as they approach the far...
Back
Top