Help understanding NMOS waveforms

[jendrix]

Hello,

I have doing an example simulation on microwind of an nmos device. This has a clock signal at the gate and at the drain, though they are at difference frequencies. I'm not sure what the S1 is referring to in this diagram

http://imgur.com/a/B9Nes

Is it the current through the device, it says it is voltage vs time but as I understand it, when a transistor is on there is little voltage across it? But in this scenario S1 is almost the same as the gate voltage?Thanks

 

[jaydnul]

Is it the current through the device, it says it is voltage vs time but as I understand it, when a transistor is on there is little voltage across it? But in this scenario S1 is almost the same as the gate voltage?

s1 is likely the voltage at the source with respect to ground, not respect to the drain. Do you have the circuit diagram?

 

[jendrix]

s1 is likely the voltage at the source with respect to ground, not respect to the drain. Do you have the circuit diagram?

Hello, I was using a guide in the Microwind manual which is the same process as this video



Are we to assume that the source is connected via a resistor to ground? Because at the point ~0.2 seconds we see S1 remain high when the gate goes off, how would this be possible if there were no current running?Thanks

 

[analogdesign]

You only connect the source through a resistor to ground if you're degenerating the transconductance of the device. If you don't know what that means, don't do it.

From looking at your plots, it looks like you're making an inverter with a single nmos device. Is this correct? Without knowing how the device is connected it is hard to help.

 

[jendrix]

You only connect the source through a resistor to ground if you're degenerating the transconductance of the device. If you don't know what that means, don't do it.

From looking at your plots, it looks like you're making an inverter with a single nmos device. Is this correct? Without knowing how the device is connected it is hard to help.

Hi, thanks but I don't know the circuit unfortunately. It was an introduction to cmos design from the Microwind manual but it doesn't tell you the layout. I'll have to clarify with my teacher as you are correct, without knowing the layout it is guesswork.

Thanks anyway

 

[jaydnul]

Because at the point ~0.2 seconds we see S1 remain high when the gate goes off, how would this be possible if there were no current running?

Correct. I'm guessing it's an NMOS driving a capacitor. That would be the reason for the on/off drain voltage, to discharge the capacitor when Vd = 0. Essentially, when the cap is charged and Vd = 0, the drain becomes the source and the source becomes the drain.