Muhammad Usman said:
As i recently came to know that the energy is not travelled in the wire infect it is travelled in the space around the wire in the electrical and magnetic field (thanks to varitasium for his video) so my question is particularly related to the IC fabrication.
In IC fabrication we have micro-scale deployment of transistors and wire connections. On a single dice which is smaller than the palm has millions of transistors, so it means that the these connections and transistors have very close space to each other so at such small scale if the energy is delivered in space then it means that this energy must have interfered with the other metal connections energy so how they are able to maintain the isolation and make sure the electric and magnetic field neither interfere or degraded ?
I disagree with the Veritasium video. The energy flows into the conductor's distributed inductance and returns thru the distributed dielectric. The phase of all the continuous spectrum of a step pulse current is 180 deg out of phase between L & C.
If all the energy travelled thru the dielectric, then you could replace conductors with sparkplug wire say at 50 kohm/m vs copper at say 50mOhm/m (a million times difference. ) then the current will not change.
But it does, so this is false. A 25 kV spike will not create half a million amps. If there was no Inductance in the wire, then the Zo would be 0 and then if the source was also near 0 Ohms, it could be a million amps. But you can never have 0 inductance in a long wire. Because then the length/width ratio would also have to be 0.
The impedance depends on both the CONDUCTION current in the wire inductance and the return from the DISPLACEMENT current in dielectric from the change in E-Field. It takes both L&C with their respective lossy resistance to transfer the energy in a transmission line with a characteristic impedance of Zo.
$$Z_o= \sqrt{\frac{R_s+L}{G_p+C}}$$
None of the energy is stored in conductor resistance, but it is all stored in +/- reactance, namely the distributed inductance and capacitance so the energy is equal in both elements but out of phase by 180 degrees with respect to each other. Thus over one cycle of all frequencies the reactance cancels out before the reflections (if they occur).
So the Zo initially behaves like pure lossless resistance if you ignore Rs, Gc and the load until the reflection occurs and all energy is shared in the distributed L & C equivalent lumped element equivalent circuit.
The propagation delay in a silicon dielectric might be around 15 um / ps so for < 1 um CMOS the path length is not the cause of the delay rather it is the junction capacitance from lower RdsOn and gate gaps. Thus the breakdown voltage perhaps of 75kV/mm or 75V/um you have a severe deionization challenge when depositing 5 nm gap CMOS!! This is one of the major challenges in yields not just from lithographic resolution but from controlling the e-fields to prevent junction arcs or breakdown in sub-microsec times.
Just like PCB's EMI crosstalk exists and conductor orientation and metalization coplanar ground tracks will reduce driver internal emissions as well as layer optimizations.