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How to understand design layout (VLSI)

  1. Sep 14, 2013 #1
    i am a beginner and i am learning cmos design technique .. i found this layout (attached) and i am not sure how to decompose and understand it - like what function is it implementing and how.. if anyone can help -----
     

    Attached Files:

  2. jcsd
  3. Sep 14, 2013 #2

    phyzguy

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    It's an SR NOR latch - the schematic is shown at this site. Are you familiar with MOS transistors at all? If not, this youtube tutorial should explain the basics. In this layout, the following colors are used:

    Red - Poly gate
    Orange - P+ Diffusion
    Green - N+ Diffusion
    Blue - Metal-1
    Filled Aqua squares - contacts that connect the Metal-1 to the poly and diffusion layers.

    Try tracing out the layout and matching it to the schematic of the SR latch. If you have more questions, ask!
     
  4. Sep 14, 2013 #3

    analogdesign

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    Phyzguy is right. This latch would be used, for example, as the sense amp in an SRAM.

    Tracing it out is the way to go. Start by following the gates (red lines) and see where they cross diffusions to create transistors. Keeping in mind that two devices often share a diffusion.

    Also, the dotted blue line around the top devices is a N-Well. This is a p-substrate process (I know that because the nmos devices on the bottom of the layout are implemented in the substrate and not in a well).

    The square near the VDD label is a well contact and the square near the GND label is a substrate contact. These are needed to reduce the resistance between the circuit and the well/substrate to mitigate latch-up.

    Good luck! This is a good circuit to get started on!
     
  5. Sep 14, 2013 #4
    @phyzguy :) yep i know about mos ... but i am not familiar with layout designing :( i know the basics but i dont know how to back trace it !!! let me go through the materials u provided and then i will ask again..
    @analogdesign :: i absolutely second you :) tracing is the way.. but thats where i am weak at. i am learning..

    can any of you please show me the transistor design ?? just simple handsketch will do. so that i can compare with this layout..
     
  6. Sep 14, 2013 #5
    here is what i was able to figure out of the circuit ... can you guys have a look and tell me whether i am right or wrong?? the PUN is of pmos and PDN is of nmos.. sorry for the bad sketch.. :(
     

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  7. Sep 14, 2013 #6

    analogdesign

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    I think you got it! Good job. Try to draw it a bit more in the standard way and how it works will be more clear to you.
     
  8. Sep 15, 2013 #7

    phyzguy

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    Looks good to me, too. You might try learning how to use a schematic editor to draw the schematics. There are several free open-source ones to choose from.
     
  9. Sep 15, 2013 #8
    :) if its not a big trouble then can u please show me the standard model of it ? i want to compare and learn .. a hand drawn one like me will be good enough...
    EDIT: please have a look at it.. is this how the standard diagram should be?
     

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    Last edited: Sep 15, 2013
  10. Sep 15, 2013 #9
    please tell me the names..i will download and start working on them... i have access to cadence in my uni but that i am absolutely noob at (maybe i will be able to handle it by the end of this term)!
     
  11. Sep 15, 2013 #10
    Question: does one require a good background in digital electronics to do this type of design? There is a graduate class at my university that offers a course in this, but the description never indicated that such was necessary.
     
  12. Sep 15, 2013 #11

    phyzguy

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    If you have access to Cadence, you should use that. Everyone starts off as a beginner. Try entering the schematic you drew, and then you will be less of a beginner.
     
  13. Sep 15, 2013 #12

    analogdesign

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    No. Physical layout in industry is often done by people with AA degrees (or a BS at most). It's important designers know how to do it and what's important however.

    I do my own layout because my organization is not large enough to have dedicated layout staff.
     
  14. Sep 15, 2013 #13

    analogdesign

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    Looks good! You got it.

    I agree 100% if you have Cadence Virtuoso use it. It completely dominates the industry. I have it open in another window right now. :)
     
  15. Sep 15, 2013 #14

    dlgoff

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  16. Sep 15, 2013 #15

    meBigGuy

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    I one had a picture of me drawn on a chip (long story). One company I worked with had a policy against signing chips so the designers put their initials in metal with voltages such that it would show up on an e-beam prober.

    Cadence has a steep learning curve in that you have to almost be an expert to do anything. Don't let that frustrate you since the end result is a very rich toolset. Just pray you never have to learn their SKILL programming language.
     
  17. Sep 15, 2013 #16
    thank you both for helping me :) seems like you guys are professionals in this field :) (one doesn't simply keeps cadence open in next window :D )
    one last question - how did you guys know it was SR (nor)latch? is it pure experience or there's some technique to quickly understand the underlying functions ???
     
  18. Sep 15, 2013 #17

    meBigGuy

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    My transistor level layout skills are zip. I couldn't have drawn the schematic. But once the schematic is drawn, the circuit topology is familiar.
     
  19. Sep 15, 2013 #18

    analogdesign

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    I have a lot of design and layout experience (I'm a professional IC designer). As you study more, you'll find that there are only a relatively small number of primitive circuit structures and you will learn to recognize them. More complex structures are made by connecting simpler structures (like NOR latches).

    I knew it was a NOR latch by tracing the circuit visually. I have enough experience that I didn't have to draw it on paper.
     
  20. Sep 15, 2013 #19

    analogdesign

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    Cool about the picture! Most companies have policies against signing chips.

    Cadence certainly does have a steep learning curve. It's a complete train wreck. SKILL isn't *that* bad, since it is based on Lisp. I prefer the Mentor tools for simulation (but Cadence for design entry). One benefit of Mentor tools is they can be scripted using TCL which is a little less crazy-making than SKILL.
     
  21. Sep 16, 2013 #20

    phyzguy

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    I used to work in IC process development, so I have a lot of experience reading and drawing physical layout. I knew it was a pair of NOR gates, since the PMOS were in series and the NMOS in parallel, so from there it was clear it was an SR latch, Also, the node names (S,R,Q,Q') were a dead giveaway.
     
  22. Sep 26, 2013 #21
    @analogdesign & @phyzguy ::
    here am i with a few more questions i hope you will be kind enough to help me with. i believe you both have understood by now that i am taking the vlsi design course because of my previous questions :) the problem is professor is super busy and the TAs are not helpful enough :( so i feel like asking you guys...
    here it is,
    i have attached the screenshot of my 2:1 MUX using 3nand and 1inverter. now , i am quoting the exact question "The circuit given has three inputs. Both the delay and power consumed by the circuit
    depends on the input pattern you apply at the input. What is the worst case pattern for delay?
    For power?" ---- i am absolutely confused... if you guys could help me then it will be really great..
    regards
     

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  23. Sep 26, 2013 #22

    analogdesign

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    Hi dafaq,

    I'll give you two thoughts. First, for delay, look at your circuit and think about the paths the signals have to go through. If S_IN switches, for instance, to get to the output the signal has to go through the inverter and then the NAND gate i2 and finally the NAND gate i3. So it must propagate through an inverter and two NAND gates. If S_IN is constant and A_IN changes instead, before the output changes the signal must go through I1 and I2 only. Do you see the difference? The delay from the A_IN input to the output is less than S_IN to the delay. Therefore, patterns that do not include S_IN switching will be faster (they will have less delay).

    As for power, a CMOS gate ideally only consumes power when it is switching, so this is similar to delay. THe patterns that make the most gates switch their states will consume the most power.

    In practice, your standard cell library documentation would have typical and worst case delays for different temperatures and you could add them up to find the worst case delay for your mux. The documentation would have similar information for power.
     
  24. Sep 26, 2013 #23

    meBigGuy

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    The trick about power is that some patterns will glitch the output when the selector switches (depends on the input state), thereby consumming extra power because of the extra switching. I'll let you discover the pattern.
     
  25. Sep 27, 2013 #24
    @both big guys :: considering the delay -- umm.. as far i know - multiplexers are used to select the input lines only. the input values are already available in the input ports and we dont really change them, we just vary the select patter (S) to check which input will go to the output. in my diagram, lets assume i have 0 in A and 1 in B and the S' is connected to the bottom NAND gate. if i assume logic 1 is true and s'=0.. in that scenario if i want to select line 1 for the output then i will simply provide 1 as select value and if i want line 2 for output then i will have to change select value to 0 so that s'=1 and the lower NAND is active. so how i see is - my worst delay will be then when i am to use the network which contains more number of logic elements. am i right? so the worst delay patter will be when i switch my select from 1 to 0 for selecting the lower input as the final output of the mux. is my answer correct?
     
  26. Sep 27, 2013 #25

    meBigGuy

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    The longest path is certainly the path through the inverter, but whether H-L or L-H is the slowest depends on the characteristics of the gates (H/L vs L/H propagation) and the input values.
     
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