How to understand design layout (VLSI)

[dafaq]

@phyzguy: i think the PUN is implementing (B+S).(A+S')
is it so?

 

[dafaq]

but i have no idea what this circuit implements ! i mean what's this circuit actually is (definitely not multiplexer or adder or things like that) ..

 

[phyzguy]

@phyzguy: i think the PUN is implementing (B+S).(A+S')
is it so?

I think this is wrong. Try making a truth table and comparing it to the truth table of some of the common 2-input functions you mentioned.

 

[dafaq]

@phyzguy
i made the truth table.. have a look.. but i can't really match this with something i remember.. can you please remind me? :( besides, what will be the worst case delay input transition ?

 

[phyzguy]

@phyzguy
i made the truth table.. have a look.. but i can't really match this with something i remember.. can you please remind me? :( besides, what will be the worst case delay input transition ?

When S = 1, Out = A. When S = 0, Out = B, so S selects A or B. What would you call this?

 

[dafaq]

No kidding! How could have i even overlooked that! Mux!
I feel stupid now..:banghead:
Thank you..

 

[dafaq]

guys :) i am to design a one bit accumulator.. i am doing the full added part, i am done with schematic and layout...but my design can't pass the LVS check T_T
i don't understand where the error is.. i am attaching the layout, schematic and the LVS repot along with, please have a look and tell me why this discrepancy.. i know reading from the layout is hard.. still if you experienced people can assist me then it would be a great help..

 

[phyzguy]

I don't know - it's really hard to see much on the plots you sent. But look at what the LVS is telling you. It found an extra net, and it didn't find two of the MN instance (presumably an NMOS transistor). So you are likely missing a connection somewhere in the NMOS devices - maybe a contact or via is missing? As a last resort, you can break it into pieces and LVS each piece separately until it passes, then put them together.

 

[dafaq]

let me try again, here is the link of the layout and i annotated which part does what..
here are the links

http://tinypic.com/view.php?pic=jpwnrb&s=5#.UnEZIRA4kUs

http://tinypic.com/r/107q6au/5

please have a look at them and see if they are correct or not.. in the mean time i will try to redo the layout...
:( it is so strenuous

 

[dafaq]

there was annotation error in the stick diagram of the carry generator, i updated it..

 

[phyzguy]

Are you sure the schematic is correct? have you simulated the schematic? If not, the error could be in either one.

Another question. If I start in the lower left, and move to the right, the second piece of poly over is a complex shape that goes up and has two stripes at the top. I don't see a contact to it anywhere. Is it there, and if so, where?

 

[dafaq]

yep, have simulated the schematic and it seems to be working fine...
for the poly, that's Q, i just used that to route the signal because there's no space to route all the signals using M1 and M2.. i just shorted the poly of Q (in Carry generator) to two of the nMOSs of the Sum generator parts. isn't just shorting them okay or i have to explicitly place contacts even if the two layers are same? :(

 

[phyzguy]

What about the spot I circled in green in the attached pdf? Shouldn't there be a via there to connect that source region up to metal-2 and then to the supply?

 

[dafaq]

T_T there should be ! i forgot it somehow ! :(
i connected that, still getting lvs error but not so much as before.. i am attaching the new lvs report...

 

[dafaq]

here it is

http://tinypic.com/r/ofzvc6/5

 

[phyzguy]

Now see that you have the right number of nets and the right number of transistors, but the layout has two extra ports. That means somewhere you have two ports that you think should be connected that aren't. You should be able to find that quickly. Where are the ports of the SP*** subcircuits, and are they all connected like they should be?

 

[dafaq]

whoao.. now that's interesting ! let me see.. -_-
dont go anywhere ! :)

 

[dafaq]

i fixed the number of ports.. actually i directly connected outputs of the inverts in the schematic !
so when i specified the inverter's output ports they threw errors.. i have a different error now.. i will upload the lvs report
1 min please

 

[dafaq]

this is the new lvs error report
http://tinypic.com/r/2cen2ao/5

have a look please

 

[phyzguy]

I don't know. It's finding one subcircuit with four pins, and not finding one with five pins, so somehow a pin is missing. Are you sure the poly with no contacts that I highlighted earlier is OK? Normally you would connect all of the poly to metal in order for them to be considered ports. Will the LVS consider that piece of poly as a port? You said that piece of poly is Q - is Q a port of the entire circuit? Another question - have you labeled the ports? LVS works a whole lot easier if you label the ports so the software can find them.

 

[dafaq]

so, should i use labels instead of wires to draw the schematic?

 

[phyzguy]

No, it's fine the way it is. I'm just saying that you can add labels to the internal nodes on your schematic and on your layout, and then when there is a port missing, you know which one is missing without having to look through the entire thing trying to figure it out.

 

[dafaq]

do u have any idea why it is saying "power net missing in source" ? the first error right under the incorrect sign!

 

[dafaq]

http://tinypic.com/r/2me3fbc/5
what are the meaning of these ! :(

 

[phyzguy]

Sorry, I don't know enough about your LVS tool to know the answer. It seems to not find the power net in the schematic, but it appears to be there. Perhaps you need a specific label on Vdd and Vss? Try reading the LVS manual.

 

[dafaq]

hi,
i was a bit busy with all these so couldn't reply sooner, i figured the problem and fixed it. i had to use separate pin instead of using explicit vdd and gnd instances. here is my final layout, have a look and say if it looks good or not :)
i am attaching the jpg with changed extension as pdf. download it and change the pdf format to jpg and it will be good enough :)
thanks for ur help... ^_^

 

[phyzguy]

Congratulations on sticking with it until it passed. It looks OK to me. I see you got rid of those long poly runs, which are resistive and will slow things down. I see you also now have everything labeled. Did the labeling help with deciphering the LVS output?

 

[dafaq]

yep..labeling did help a lot...without labels it is very tough to read the layout (almost impossible) ... i stuck to ur advices till the end and i was finally able to make things right.. thank u so much ^_^ and yep, i got rid of those poly, i didnt like them anyway, previously i used them just because i didnt have enough room to route my signals separately.. :)

 

[dafaq]

hellowwww :)
here i am again ^_^ with doubts... (as always)
please have a look at the circuit , it is i believe a dual rail domino gate, i want to determine the output Y and Y'.. i used hspice to be sure that i didn't make any silly mistake. here is the hspice output in cscope.. (i used vector file to give inputs to A and B and the input vectors of A and B are like - 00,01,10,11,00,00,00,01,10,11,)
now, the truth table of this compound gate is -

A B Y Y'
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 0

i am a bit confused what logic it actually implements... the Y is always equal to A, and Y' is equal to B for first 3 inputs.. can u please throw some insight ? :)

 

[phyzguy]

I'm not sure exactly what it is either, but your analysis is incomplete. If A and B are both low, then Y and Y' are both low as you have it. However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high. It is not simply a combinational logic circuit - because of the internal feedback it can store data from the past history as well.