How to understand design layout (VLSI)

  • Thread starter Thread starter dafaq
  • Start date Start date
  • Tags Tags
    Design Vlsi
Click For Summary

Discussion Overview

The discussion focuses on understanding the layout of a CMOS design, specifically an SR NOR latch. Participants explore how to decompose the layout to identify its function and the components involved, including the use of various diffusion and metal layers. The conversation includes technical explanations and requests for visual aids to aid comprehension.

Discussion Character

  • Exploratory
  • Technical explanation
  • Conceptual clarification
  • Debate/contested
  • Homework-related

Main Points Raised

  • One participant expresses uncertainty about how to understand and decompose the layout of an SR NOR latch.
  • Another participant identifies the layout as an SR NOR latch and provides color-coded explanations of the different layers used in the design.
  • Some participants suggest tracing the layout to match it with the schematic to gain a better understanding.
  • There are discussions about the importance of well contacts and substrate contacts in reducing resistance and mitigating latch-up.
  • Participants share their experiences and suggest using schematic editors to improve drawing skills.
  • Questions arise about the necessity of a strong background in digital electronics for layout design, with differing opinions on the level of expertise required.
  • Some participants share their personal experiences with using Cadence software and its learning curve.
  • There is a request for a standard model of the SR latch to compare with the participant's hand-drawn version.
  • One participant mentions that recognizing circuit structures comes with experience and familiarity with common designs.

Areas of Agreement / Disagreement

Participants generally agree on the identification of the layout as an SR NOR latch and the importance of tracing the layout for understanding. However, there are varying opinions on the required background knowledge for layout design and the learning process associated with using design software.

Contextual Notes

Some participants express limitations in their understanding of layout design and the need for further study and practice. The discussion reflects a range of experience levels among participants, from beginners to professionals.

Who May Find This Useful

Individuals interested in CMOS design, VLSI layout, and those seeking to improve their understanding of digital electronics and circuit design may find this discussion beneficial.

  • #61
? " However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high." ---> i see only one situation when both are 1 ! Y & Y' being 1 and 0 respectively... -_-
what am i missing.. T_T
 
Engineering news on Phys.org
  • #62
dafaq said:
? " However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high." ---> i see only one situation when both are 1 ! Y & Y' being 1 and 0 respectively... -_-
what am i missing.. T_T

Isn't it completely left/right symmetric? If there is a state with Y high and Y' low, doesn't there have to be a corresponding state with Y low and Y' high?
 
  • #63
:cry: but how do i find that ! for two inputs i already have used all possible 4 combination vectors.. T_T i have no clue how to find the state u r talking.. i do understand theoritically what u r saying but no clue how to get that practically... :(
 
  • #64
dafaq said:
:cry: but how do i find that ! for two inputs i already have used all possible 4 combination vectors.. T_T i have no clue how to find the state u r talking.. i do understand theoritically what u r saying but no clue how to get that practically... :(

You need to force the simulator into the correct state by introducing some left/right asymmetry. Try adding a small capacitor to one of the two cross-coupled gates (the gates of the middle NMOS devices). With the capacitor on the left it should go one way, and with the capacitor on the right it should go the other way.
 
  • #65
phyzguy said:
You need to force the simulator into the correct state by introducing some left/right asymmetry. Try adding a small capacitor to one of the two cross-coupled gates (the gates of the middle NMOS devices). With the capacitor on the left it should go one way, and with the capacitor on the right it should go the other way.

umm..here is what i found in my textbook..have a look.. it says dual rail domino cannot have both inputs high at the same time... check the image i attached along as pdf (just change the extension to .jpg from .pdf) and see the table... if i take that for granted then i believe the circuit is kind of like multiplexer... Y always follows A and Y' follows B... what do u say?
 

Attachments

Similar threads

Final semester project ideas using CMOS VLSI?
  • · Replies 11 ·
Replies
11
Views
2K
Where Can I Find Electrical Design Case Studies?
  • · Replies 11 ·
Replies
11
Views
2K
What is Baseband RF communication?
  • · Replies 5 ·
Replies
5
Views
2K
Combining Digital and Bipolar Tech for VLSI Layout Project
  • · Replies 1 ·
Replies
1
Views
2K
Getting a High Speed Synchronous N-Channel MOSFET Driver working right
  • · Replies 39 ·
2
Replies
39
Views
6K
Designing a 24-100V to 12V Buck Converter Circuit
  • · Replies 32 ·
2
Replies
32
Views
6K
How can I learn to use Cadence for PCB design?
  • · Replies 4 ·
Replies
4
Views
2K
What Is the Fundamental Unit of CCD/CMOS Sensors Called?
  • · Replies 25 ·
Replies
25
Views
2K
Cadence Inverter layout lambda based design
  • · Replies 1 ·
Replies
1
Views
1K
Engineering Job Positions for US Engineering Job Market for VLSI Design Focus Grad
  • · Replies 1 ·
Replies
1
Views
2K