How to understand design layout (VLSI)

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The discussion focuses on understanding the layout of an SR NOR latch in CMOS design. Participants emphasize the importance of tracing the layout to match it with the schematic, highlighting the use of color coding for different components. They recommend using Cadence for design entry, noting its steep learning curve but extensive capabilities. Questions arise about the necessary background in digital electronics for layout design, with responses indicating that practical experience is often more valuable than formal education. Finally, a query about analyzing a 2:1 multiplexer leads to insights on delay and power consumption based on input patterns, stressing the significance of signal paths in determining performance.
  • #61
? " However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high." ---> i see only one situation when both are 1 ! Y & Y' being 1 and 0 respectively... -_-
what am i missing.. T_T
 
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  • #62
dafaq said:
? " However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high." ---> i see only one situation when both are 1 ! Y & Y' being 1 and 0 respectively... -_-
what am i missing.. T_T

Isn't it completely left/right symmetric? If there is a state with Y high and Y' low, doesn't there have to be a corresponding state with Y low and Y' high?
 
  • #63
:cry: but how do i find that ! for two inputs i already have used all possible 4 combination vectors.. T_T i have no clue how to find the state u r talking.. i do understand theoritically what u r saying but no clue how to get that practically... :(
 
  • #64
dafaq said:
:cry: but how do i find that ! for two inputs i already have used all possible 4 combination vectors.. T_T i have no clue how to find the state u r talking.. i do understand theoritically what u r saying but no clue how to get that practically... :(

You need to force the simulator into the correct state by introducing some left/right asymmetry. Try adding a small capacitor to one of the two cross-coupled gates (the gates of the middle NMOS devices). With the capacitor on the left it should go one way, and with the capacitor on the right it should go the other way.
 
  • #65
phyzguy said:
You need to force the simulator into the correct state by introducing some left/right asymmetry. Try adding a small capacitor to one of the two cross-coupled gates (the gates of the middle NMOS devices). With the capacitor on the left it should go one way, and with the capacitor on the right it should go the other way.

umm..here is what i found in my textbook..have a look.. it says dual rail domino cannot have both inputs high at the same time... check the image i attached along as pdf (just change the extension to .jpg from .pdf) and see the table... if i take that for granted then i believe the circuit is kind of like multiplexer... Y always follows A and Y' follows B... what do u say?
 

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