What Is a Complemented Voltage Source in an Inverter Circuit?

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Homework Statement

[/B]
I am studying a book related to digital integrated circuits and there is something I cannot understand.
The book starts by explaining two basic building blocks of digital integrated circuits: the inverter and the non-inverter. My question is about the inverter.

It says the above figure is an ideal logic inverter. It operates with a single power source V_cc. The logical 1 output voltage is ideally at the V_cc and the logical 0 output voltage is ideally at the ground. For the inputs, logical input 0 is represented by the voltage range 0<= V_in < (V_cc)/2 and the logical input 1 lies between the range (V_cc)/2 < V_in <= V_cc. After that the following figure is provided.

According to the text, the input can be modeled as a parallel resistance and capacitance, and the output is modeled as resistance in series with a complemented voltage source. My question is that what is a complemented voltage source and how does the above circuit work as an inverter?

Homework Equations

The Attempt at a Solution

 

[Wee-Lamm]

According to the text, the input can be modeled as a parallel resistance and capacitance, and the output is modeled as resistance in series with a complemented voltage source. My question is that what is a complemented voltage source and how does the above circuit work as an inverter?

Homework Equations

3. The Attempt at a Solution [/B]

A complemented voltage source means the output state will be 'not input'. If input is high, output will be 'not high' (or low). If input voltage is low, output will be 'not low' (or high). If you like binary better; if input = 1 then output = 0. if input = 0 then output = 1.

Figure 1 is the schematic symbol of a digital logic Not gate, which is an inverter.

It says the above figure is an ideal logic inverter. It operates with a single power source V_cc. The logical 1 output voltage is ideally at the V_cc and the logical 0 output voltage is ideally at the ground.

Vcc is a reference voltage which is higher than ground. Ideally, if Vin is > Vcc/2, Vout will = near ground. If Vin < Vcc/2 then Vout will = Vcc.

For the inputs, logical input 0 is represented by the voltage range 0<= V_in < (V_cc)/2 and the logical input 1 lies between the range (V_cc)/2 < V_in <= V_cc. After that the following figure is provided.

The "Logical" inputs are not physical inputs, but binary states the single input can take where High = 1, Low = 0.

0<= V_in < (V_cc)/2
Binary 0 is more than 0 volts but less than vcc/2

(V_cc)/2 < V_in <= V_cc
Binary 1 is more than vcc/2 but less than or equal to vcc

As a built in filter, If Vin < 0, nothing was received. If Vin is > vcc, nothing was received but noise.For practice, presume a value of 3 volts at vcc, and vin as a value between 0 and 4, fractions allowed. Solve for several values of Vin to determine whether input was high or low. Output state will always be opposite of input state as this is a logic inverter, or NOT gate.

 

[hitemup]

@Wee-Lamm

If we can change the voltage from high to low and vice versa by using a dependent voltage source, then what's the use of capacitor and resistors in the circuit? One more question: where is v_cc in the second figure? I understand how a not gate works but I couldn't see what is happening at the circuit level.
For example, how is output 3V when input is 1V if V_cc = 3V.

 

[Wee-Lamm]

For the bits in the second image;
I would say that the RC network at the input creates a phase shift between current and voltage, which then goes through the rectifier (diamond) to flip the polarity of half the cycle, and R2 filters the surge current from C1's discharge states. This should clean up the signal at Vout to reduce the number of results that may otherwise be ignored as potential noise.

If you printed each image on overhead transparencies such that the triangles were the same size in both, then layered them such that the triangles lined up, it might make more sense. These images are partially schematic and partially logical layout. If you were building the IC you would need to see all the connections and such inside it. For using the gate in a circuit, it is enough to know it works. :-)

 

[gneill]

If we can change the voltage from high to low and vice versa by using a dependent voltage source, then what's the use of capacitor and resistors in the circuit? One more question: where is v_cc in the second figure? I understand how a not gate works but I couldn't see what is happening at the circuit level.

While the first image depicts an ideal inverter, the second shows a conceptual model for a practical implementation. It is not a full schematic, but rather an equivalent model depicting the important features of such an implementation. In it, the power to operate the blocks of the model is just assumed to be there and not depicted.

In the real world, components are not ideal; Inputs do not have infinite impedance, and outputs do not have zero output resistance. This model shows how they relate to a practical implementation of an inverter.

Practical design (particularly at high frequencies as in high speed digital logic circuits) requires that things like input and output impedance be taken into account. They determine things like device fanout (how many other gates can the output of one gate drive), the rise time of a change of logic level (hence switching delays), and whether to worry about signal reflections on the data paths between chips due to impedance matching issues. Circuit board traces act like transmission lines at high frequencies. Capacitance associated with inputs delays logic level transitions, rounding off square signal edges and introducing timing delays. The nice sharp-edged logic signals of a theoretical design can become quite a mushy mess and introduce unexpected race conditions or timing errors in what was a nice synchronous circuit design on paper.

 

[NascentOxygen]

Vcc is a reference voltage which is higher than ground. Ideally, if Vin is > Vcc, Vout will = near ground. If Vin < Vcc then Vout will = Vcc.

Is this what you intended to write?

EDIT: I have gone back and included your corrections

 

[hitemup]

@gneill
Thank you for your comprehensive explanation about the input and output impedances and what they are good for. I understand these components avoid some bad conditions that may occur. However, I still wonder how the invertion is done in a NOT gate in the second figure, or I don't know if the invertion should be understood from that image. Could you please explain that part also?

 

[berkeman]

IMO it's better to just look at the equivalent circuit for a simple inverter, rather than try to understand it based on some abstract circuit model...

http://www-tcad.stanford.edu/~fmr/research/mixedmode/mmEGinvExample1.gif

 

[gneill]

@gneill
Thank you for your comprehensive explanation about the input and output impedances and what they are good for. I understand these components avoid some bad conditions that may occur. However, I still wonder how the invertion is done in a NOT gate in the second figure, or I don't know if the invertion should be understood from that image. Could you please explain that part also?

The equivalent model shows a controlled source that drives the output. It is specified that it produces the logical negation of what is "read" at the input. Note that the model does not include any details about how the input is read and interpreted, nor how that information transmitted to the controlled source. For that kind of detail you need to look at an actual implementation of a NOT gate, as @berkeman suggests.

 

[donpacino]

IMO it's better to just look at the equivalent circuit for a simple inverter, rather than try to understand it based on some abstract circuit model...

http://www-tcad.stanford.edu/~fmr/research/mixedmode/mmEGinvExample1.gif

many schools will teach "simple circuits" using just passive components and op-amps first. They don't touch transistors until later on in the curriculum. It is possible OP does not understand what a FET is.