Keeping a count of user button pushes --

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This discussion focuses on implementing a button push counter using the Altera DE2 Development Board and a 74163 counter. The primary issue addressed is the need for an edge detector and debounce circuit to ensure accurate counting of button presses. The counter should only increment once per button press, which requires a one-shot pulse generator to create a single clock duration pulse for the count-enable signal. Proper synchronization of the button input with the internal clock is essential to avoid counting mechanical bounces.

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  • Understanding of 74163 counter operation
  • Knowledge of edge detection and debounce circuit design
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Electronics engineers, FPGA developers, and hobbyists working on digital counter projects or button interface designs.

thisguy928
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Hi, I'm using an Altera DE2 Development Board. I'm creating a counter that counts the number of times a user pushes a button. I'm using 74163 counter since I need to count 0-9 and I think it's easier to control. I must have it running on an internal clock. However, my counter didn't seem to be working to perfectly. when the button is pressed, P and T are true and the counter starts counting but it counts from 0-9 changing on the edge of clock. How am I able to implement this? how can I keep the single ou out count after the button is pressed and held even if the clock is 'clockkng'?
 
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You will need to implement an edge detector and debounce circuit before feeding the counter.

I'm assuming that you mean that you have implemented the logic of a 74163 inside of the FPGA but the same thing applies if you are using an external discrete 74163.

Edge detect & debounce are easy to implement in your FPGA.
 
You are having one of 2 problems, I think, but I'm not sure which.

Either you are feeding the button into the counter clock input, in which case you are counting the mechanical bounce of the button (like emi guy said). Or, you are feeding a clock to the counter (which what I think you are doing) and want the count-enable signal to only allow 1 count per button press. For that to happen, the count enable signal can only be 1 clock in duration.

Either way, you must first debounce the switch.

Then, you must make a 1-shot circuit that causes 1 pulse that is 1 clock in duration, for each button press, to feed to the counter's enable input. It can be tricky because you have to synchronize the asynchronous input of the button to the internal clock using a meta-stable proof double synchronizer (look it up). That can be a 3 flip-flop shift register clocked off the internal clock that is fed by a high true button press signal. You use AND gate off the Q of the 2nd flop and the QN of the third flop to feed your count-enable (if it is high true). (or you can use low true and change the output detector. Or, you can detect the trailing edge of the button press, or whatever you want.)

The signal into the shift register (or, synchronizer and pulse generator as you will) must first be debounced. You can look that part up. There are lots of ways, so research it and then ask questions.
 

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