Comp Sci K's Moore Machine: Check it Out!

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The discussion focuses on the correctness of a Moore Machine example shared by Zulfi. There are concerns about the labeling of states and the matching of outputs to rewards, indicating a mix-up in the definitions. Participants suggest clarifying the machine's reset state and ensuring all states are named for better coding practices in VHDL or Verilog. Zulfi acknowledges these points and agrees to make the necessary corrections. The conversation emphasizes the importance of clear definitions and accurate labeling in machine design.
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Homework Statement
A computer game generates ‘1s’ and ‘0s’. These are associated with awards. The first ‘1’ (i.e. the first 1 of an uninterrupted sequence of 1's obtained by continuously running the program several times such that each execution generates a 1 output in that set of executions) results in 4 awards but the remaining 1’s do not result in any award. On the other hand, each odd numbered 0 results in 2 points and each even numbered 0 does not get any award. For the output 011100001011.. of executions results in awards 2400202024240……

Can we construct a transducer to do the above computation? If yes show it. Otherwise explain why?
Relevant Equations
No Eq.
Kindly see my attached Moore Machine.

Is it correct?

Zulfi.
Two point one point Machine.jpg
 
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Something went wrong with your example, here both together:
011100001[/color]011
2400202024[/color]240

"Odd numbered 0" refers to the length of a continuous run of zeros, or the absolute position in the string? Your machine does a weird mixture of the two. The labels don't match the rewards you discuss before.
 
Hi,
Sorry for wrong last statement. Correcting the last statement of question:

"For the output 0111000001011.. of executions results in awards 2 4 0 0 2 0 2 0 2 4 2 4 0……"

2 4 0 0 2 0 2 0 2 4 2 4 0……
0 1 1 1 0 0 0 0 0 1 0 1 1...

For 0s we are counting from the beginning of the string.

Thanks for your response.

<The labels don't match the rewards you discuss before. >

Yes you are right.

I would correct it.

Zulfi.
 
Which state does a Reset (or start) take the machine to? It's best to always show that explicitly... :smile:
 
Hi,
Thanks. I would show this. Upper left, I have to put a => symbol before it. Thanks.

Zulfi.
 
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And also be sure to name all of your states, not just the ones that update the output. When you code this in VHDL or Verilog, each state will need to have a name. :smile:
 

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