LTSpice Clock signal distortion

[salil87]

Hi
I made a counter using Dflop in Ltspice. But when I am using the count bits as signal to other circuits the clock signal is getting distorted. Why is this happening? How can I overcome this problem?
Thanks
Salil

 

[analogdesign]

You might be loading the Dflops too much. Try putting buffers between the counter output bits and whatever circuit they are driving.

 

[jrive]

can you post your LTSpice schematic and results showing the distorted clock?