LTSpice Clock signal distortion

  1. Hi
    I made a counter using Dflop in Ltspice. But when I am using the count bits as signal to other circuits the clock signal is getting distorted. Why is this happening? How can I overcome this problem?
  2. jcsd
  3. analogdesign

    analogdesign 834
    Science Advisor

    You might be loading the Dflops too much. Try putting buffers between the counter output bits and whatever circuit they are driving.
    1 person likes this.
  4. can you post your LTSpice schematic and results showing the distorted clock?
Know someone interested in this topic? Share this thead via email, Google+, Twitter, or Facebook

Have something to add?

Draft saved Draft deleted