MOS capacitance when Vgs is negative

AI Thread Summary
When Vgs goes negative in an NMOS device, the channel becomes filled with holes due to the p- substrate, leading to the observation of Cox capacitance. The capacitance between gate and source/drain (Cgs and Cgd) is reduced as the device enters depletion mode, with Cgb in series with Csb and Cdb. As Vgs decreases further, the device transitions into accumulation mode, where the gate-bulk capacitance increases back to inversion mode values. In accumulation mode, the drain and source are effectively shorted through the channel, causing Cgb, Cgd, and Cgs to connect in parallel. Overall, the behavior of MOS capacitance under negative Vgs is influenced by the transition between depletion and accumulation modes.
iVenky
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I have a question on what happens to MOS capacitance Cgs+Cgd, when Vgs goes negative in the NMOS shown. I see that when Vgs goes negative, the channel is full of holes because of p- substrate, which means we see the Cox capacitance (without any other capacitance in series), but I am not sure if this is between Cgs (or Cgd) or Cgb. My intuition says it's between Cgb, but if that's the case, then there is no capacitance between Cgs (or Cgd), ignoring the overlap capacitance.
Attached the figure here

https://imgur.com/a/LPlIcKX
 
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iVenky said:
I have a question on what happens to MOS capacitance Cgs+Cgd, when Vgs goes negative in the NMOS shown. I see that when Vgs goes negative, the channel is full of holes because of p- substrate, which means we see the Cox capacitance (without any other capacitance in series), but I am not sure if this is between Cgs (or Cgd) or Cgb. My intuition says it's between Cgb, but if that's the case, then there is no capacitance between Cgs (or Cgd), ignoring the overlap capacitance.
Attached the figure here

https://imgur.com/a/LPlIcKX
The capacitance (between gate and source/drain) of NMOS in depletion is reduced because no channel mean Cgb is in series with Csb+Cdb.
with negative voltage, the capacitance is limited by Csb+Cdb, and reverse proportional to square root of voltage between gate and drain/source - because of depletion regions forming around source/drain
 
Actually when you apply a small negative voltage to the gate the device enters a depletion mode and in that mode what Trurle said is true. But then if you decease the Vgs even lower the device enter the accumulation mode and the gate-bulk capacitance increases again back to the same value that it had in the inversion mode (when Vgs>Vth). In the accumulation mode in the first approximation (neglecting the channel resistance) the drain and source are shorted through the low-resistance of the channel so all capacitors Cgb, Cgd and Cgs are connected in parallel. In a more accurate approximation you have a distributed RC-network across the channel.
 
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